IIDA MASAHIRO 飯田全広

… Alternative Names

飯田全広イイダマサヒロ

IIDA Masahiro 飯田全広

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Researcher Number	70363512
Other IDs
External Links
Affiliation (Current)	2025: 熊本大学, 半導体・デジタル研究教育機構, 教授
Affiliation (based on the past Project Information) *help	2023: 熊本大学, 半導体・デジタル研究教育機構, 教授 2017 – 2019: 熊本大学, 大学院先端科学研究部(工), 教授 2011 – 2013: 熊本大学, 自然科学研究科, 准教授 2007 – 2008: Kumamoto University, 大学院・自然科学研究科, 准教授 2006: 熊本大学, 大学院自然科学研究科, 助教授 2004 – 2005: 熊本大学, 工学部, 助教授
Review Section/Research Field	Principal Investigator Computer system/Network / Basic Section 60040:Computer system-related / Computer system / Electron device/Electronic equipment / Software
Keywords	Principal Investigator FPGA / リコンフィギャラブルシステム / 概略計算 / LSI / SNN / スモールワールド / グラフ理論 / ハイパフォーマンス・コンピューティング / ネットワーク / Graph Golf … More / ODP / Pseudo-ZDD / Cayley Graph / ASPL / グラフ処理 / System LSI / Multi-context / Partially Reconfiguration / Dynamically Reconfiguration / Data Dependent Circuit / Lowe Energy / Low Power / 回路再構成 / フィールドプログラマブルゲートアレイ(FPGA) / システムLSI / SoC / 回路再構成法 / 回路分割 / データ依存回路 / 消費電力削減方式 / 低消費電力 / ハードウェア記述言語 / GPGPU / 並列計算モデル / 仮想CGRA / 粗粒度リコンフィギャラブルシステム / プログラミングモデル / アクセラレータ / CGRA / Java / LSIテスト / ハードエラー回避 / ハードエラー検出 / ディペンダブル・コンピューティング / ハードエラー検出．回避 / 電子デバイス・機器 / ディペンダブル・コンピューティング / LSI試作 / SEU / ソフトエラー / ディペンダブルシステム / ＦＰＧＡ / 構成データ / クラスタリング / 低消費電力化 / 配線共有 / テクノロジマッピング / コンテキスト統合 / マルチコンテキスト / 設計自動化 Less

A study of SNN device using serial approximate addersPrincipal Investigator
- Principal Investigator
  
  飯田全広
- Project Period (FY)
  2023 – 2026
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Kumamoto University
A study on low delay network topology for a large scale parallel computing systemPrincipal Investigator
- Principal Investigator
  
  IIDA Masahiro
- Project Period (FY)
  2017 – 2019
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system
- Research Institution
  Kumamoto University
A Study of High Dependability Reconfigurable Logic ArchitecturePrincipal Investigator
- Principal Investigator
  
  IIDA Masahiro
- Project Period (FY)
  2011 – 2013
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Kumamoto University
Research on programming model for Reconfigurable SystemsPrincipal Investigator
- Principal Investigator
  
  IIDA Masahiro
- Project Period (FY)
  2011 – 2013
- Research Category
  
  Grant-in-Aid for Challenging Exploratory Research
- Research Field
  
  Software
- Research Institution
  Kumamoto University
A study of the integrated EDA tools for reconfigurable logicPrincipal Investigator
- Principal Investigator
  
  IIDA Masahiro
- Project Period (FY)
  2006 – 2008
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Kumamoto University
A LOW ENERGY DESIGN METHOD USING MULTI-CONTEXT RECONFIGURATIONPrincipal Investigator
- Principal Investigator
  
  IIDA Masahiro
- Project Period (FY)
  2004 – 2005
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Kumamoto University

All 2023 2019 2018 2017 2013 2012 2011 2007 2006 2005 2004

All Journal Article Presentation Patent

[Journal Article] LSI化の検討に使用するSNNシミュレータSULIの開発と評価2023
- Author(s)
  小崎裕二郎, 坂本圭, 飯田全広
- Journal Title
  
  電子情報通信学会技術研究報告
  
  Volume: 122 Pages: 107-111
- Data Source
  KAKENHI-PROJECT-23K11034
[Journal Article] Order Adjustment Approach Using Cayley Graphs for the Order/Degree Problem2018
- Author(s)
  T Kitasuka, T Matsuzaki, M Iida
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E101.D Issue: 12 Pages: 2908-2915
- DOI
  10.1587/transinf.2018PAP0008
- NAID
  130007539328
- ISSN
  0916-8532, 1745-1361
- Year and Date
  2018-12-01
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17K00082
[Journal Article] FPGAを用いたグラフストリーム処理の一検討2017
- Author(s)
  松崎貴之，尼崎太樹，飯田全広，久我守弘，末吉敏則
- Journal Title
  
  信学技報, vol. 117, no. 279, RECONF2017-38, pp. 7-12, 2017年11月.
  
  Volume: 117 Pages: 7-12
- Data Source
  KAKENHI-PROJECT-17K00082
[Journal Article] A reconfigurable Java accelerator with software compatibility for embedded systems2013
- Author(s)
  Y. Ogawa, M. Iida, M. Amagasaki, M. Kuga and T. Sueyoshi
- Journal Title
  
  Proc. International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2013)
  
  Pages: 39-44
- Data Source
  KAKENHI-PROJECT-23650018
[Journal Article] システムLSI搭載FPGA-IPコア向け物理故障検出及び回避手法2013
- Author(s)
  尼崎太樹，西谷祐樹，井上万輝，飯田全広，久我守弘，末吉敏則
- Journal Title
  
  信学論D
  
  Volume: Vol.J96-D，No.12 Pages: 3019-3029
- NAID
  40019900178
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23300017
[Journal Article] システムLSI搭載FPGA-IPコア向け物理故障検出及び回避手法2013
- Author(s)
  尼崎太樹, 西谷祐樹, 井上万輝, 飯田全広, 久我守弘, 末吉敏則
- Journal Title
  
  信学論D
  
  Volume: Vol.J96-D, No.12 Pages: 3019-3029
- NAID
  40019900178
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23300017
[Journal Article] 仮想CGRAへのJavaソフトウェアのマッピングとFPGA実装2013
- Author(s)
  小川裕喜, 尼崎太樹, 飯田全広, 久我守弘, 末吉敏則
- Journal Title
  
  信学技報 RECONF2013-47
  
  Volume: vol. 113 , no. 325 Pages: 45-50
- Data Source
  KAKENHI-PROJECT-23650018
[Journal Article] FPGA Design Framework Combined with Commercial VLSI CAD2013
- Author(s)
  Q.Zhao, K.Inoue, M.Amagasaki, M.Iida, M.Kuga, T.Sueyoshi
- Journal Title
  
  IEICE Transactions on Information and Systems
  
  Volume: Vol.E96-D, No.8 Pages: 1602-1612
- NAID
  130003370942
- Data Source
  KAKENHI-PROJECT-23300017
[Journal Article] COGRE : A Novel Compact Logic Cell Architecture for Area Minimization2012
- Author(s)
  M.Iida, M.Amagasaki, Y.Okamoto, Q.Zhao and T.Sueyoshi
- Journal Title
  
  IEICE Transactions on Information and Systems
  
  Volume: Vol.E95-D, No.2 Pages: 294-302
- NAID
  10030610468
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23300017
[Journal Article] An Easily Testable Routing Architecture and Prototype Chip2012
- Author(s)
  K.Inoue, M.Amagasaki, M.Iida, T.Sueyoshi
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E95-D Issue: 2 Pages: 303-313
- DOI
  10.1587/transinf.E95.D.303
- NAID
  10030610493
- ISSN
  0916-8532, 1745-1361
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23300017
[Journal Article] Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration2012
- Author(s)
  Y.Ichinomiya, T.Kimura, M.Amagasaki, M.Kuga, M.Iida and T.Sueyoshi
- Journal Title
  
  IEICE Transactions on Fundamentals of Electronics
  
  Volume: Vol.E95-A, No.12 Pages: 2347-2356
- NAID
  10031161369
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23300017
[Journal Article] Fault Recovery Technique for TMR Softcore Processor System using Partial Reconfiguration2012
- Author(s)
  M.Fujino, H.Tanaka, Y.Ichinomiya, M.Kuga, M.Iida, M.Amagasaki and T.Sueyoshi
- Journal Title
  
  Lecture Notes in Computer Science, Springer-Verlag Berlin Heidelberg
  
  Volume: 7439 Pages: 392-404
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23300017
[Journal Article] 組込みシステムを対象としたリコンフィギャラブルJavaアクセラレータの一検討2012
- Author(s)
  高田誠也, 尼崎太樹, 飯田全広, 久我守弘, 末吉敏則
- Journal Title
  
  信学技報RECONF2012-48
  
  Volume: vol.112, no.325 Pages: 9-14
- NAID
  110009642170
- Data Source
  KAKENHI-PROJECT-23650018
[Journal Article] A bitstream relocation technique to improve flexibility of partial reconfiguration2012
- Author(s)
  Y.Ichinomiya, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Journal Title
  
  Lecture Notes in Computer Science, Springer-Verlag Berlin Heidelberg
  
  Volume: 7439 Pages: 139-152
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23300017
[Journal Article] An Easily Testable Routing Architecture and Prototype Chip2012
- Author(s)
  K.Inoue, M.Koga, M.Amagasaki, M.Iida, Y.Ichida, M.Saji, J.Iida and T.Sueyoshi
- Journal Title
  
  IEICE Transactions on Information and Systems
  
  Volume: Vol.E95-D, No.2 Pages: 303-313
- NAID
  10030610493
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23300017
[Journal Article] COGRE: A Novel Compact Logic Cell Architecture for Area Minimization2012
- Author(s)
  M.Iida, M.Amagasaki, Y.Okamoto, Q.Zhao, T.Sueyoshi
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E95-D Issue: 2 Pages: 294-302
- DOI
  10.1587/transinf.E95.D.294
- NAID
  10030610468
- ISSN
  0916-8532, 1745-1361
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23300017
[Journal Article] A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems2011
- Author(s)
  Q.Zhao, Y.Ichinomiya, M.Amagasaki, M.Iida and T.Sueyoshi
- Journal Title
  
  IEEE Embedded Systems Letters
  
  Volume: Vol.3, Issue3 Pages: 89-92
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23300017
[Journal Article] A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems2011
- Author(s)
  Qian Zhao, Yoahihiro Ichinomiya, et al
- Journal Title
  
  IEEE Embedded Systems Letters
  
  Volume: 3 Issue: 3 Pages: 89-92
- DOI
  10.1109/les.2011.2167213
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-11J07446, KAKENHI-PROJECT-22300018, KAKENHI-PROJECT-23300017
[Journal Article] Clustering Technique to Reduce Chip Area and Delay for FPGA,2007
- Author(s)
  M.Kobata, M.Iida and T.Sueyoshi
- Journal Title
  
  Electronics and Communications in Japan 6(Vol.90)
  
  Pages: 34-46
- NAID
  110007385832
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18300015
[Journal Article] Evaluating Variable-Grain Logic Cells using Heterogeneous Technology Mapping, P.C.Diniz et.al.2007
- Author(s)
  Kazunori MATSUYAMA, Motoki AMAGASAKI, Hideaki NAKAYAMA, Ryoichi YAMAGUCHI, Masahiro IIDA, Toshinori SUEYOSHI
- Journal Title
  
  (eds.) : Reconfigurable Computing : Architectures, Tools and Applications, Lecture Notes in Computer Science (LNCS)4419, Springer-Verlag Berlin Heidelberg 4419
  
  Pages: 142-154
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18300015
[Journal Article] Evaluating Variable-Grain Logic Cells using Heterogeneous Technology Mapping2007
- Author(s)
  Kazunori MATSUYAMA, Motoki AMABASAKI, Hideaki NAKAYAMA, Ryoichi YAMAGUCHI, Masahiro IIDA, Toshinori SUEYOSHI
- Journal Title
  
  Lecture Notes in Computer Science (LNCS), Springer-Verlag Berlin Heidelberg 4419
  
  Pages: 142-154
- Data Source
  KAKENHI-PROJECT-18300015
[Journal Article] 粒度可変構造を持つ再構成論理セル向けマッピング手法の評価2007
- Author(s)
  山口良一, 中山英明, 尼崎太樹, 松山和憲, 飯田全広, 末吉敏則
- Journal Title
  
  第14回FPGA/PLD Design Conference ユーザプレゼンテーション論文集
  
  Pages: 25-32
- Data Source
  KAKENHI-PROJECT-18300015
[Journal Article] A Novel Technique to Design Energy-Efficient Contexts for Reconfigurable Logic Devices2007
- Author(s)
  H.Shinohara, H.Monji, M.Iida and T.Sueyoshi
- Journal Title
  
  IEICE TRANSACTIONS on Information and Systems 12(vol.E90-D)
  
  Pages: 1986-1989
- NAID
  110007538594
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18300015
[Journal Article] 動的再構成デバイス向け配線共有型マルチコンテキスト化手法の一検討2006
- Author(s)
  篠原拓, 木幡雅貴, 今井茂毅, 飯田全広, 末吉敏則
- Journal Title
  
  信学技法 VLD2005-100, CPSY2005-56, RECONF2005-89(2006-1) 105・42
  
  Pages: 19-24
- NAID
  10017303658
- Data Source
  KAKENHI-PROJECT-16560303
[Journal Article] Effective Clustering Technique to Optimize Routability of Outer Cluster Nets2006
- Author(s)
  Masaki Kobata, Masahiro Iida, Toshinori Sueyoshi
- Journal Title
  
  Proc.of Fourteenth ACM/SIGDA International Symposium on Fieid-Programmable Gate Arrays (FPGA2006)
  
  Pages: 229-229
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16560303
[Journal Article] FPGAのチップ面積および遅延を最適化するクラスタリング手法2006
- Author(s)
  木幡雅貴, 飯田全広, 末吉敏則
- Journal Title
  
  電子情報通信学会論文誌 J89-D
  
  Pages: 1120-1129
- Data Source
  KAKENHI-PROJECT-18300015
[Journal Article] 粒度可変構造を持つ再構成論理セル向けマッピング手法の一検討2006
- Author(s)
  山口良一, 松山和憲, 中山英明, 尼崎太樹, 飯田全広, 末吉敏則
- Journal Title
  
  電子情報通信学会技術研究報告 RECONF2006-1(2006-05) 106・49
  
  Pages: 1-6
- NAID
  110004741126
- Data Source
  KAKENHI-PROJECT-18300015
[Journal Article] CPU混載部分再構成型FPGAを用いた動的再構成システムの開発2006
- Author(s)
  坂本伊佐雄, 須崎貴憲, 柴村英智, 飯田全広, 久我守弘, 末吉敏則
- Journal Title
  
  第13回FPGA/PLD Design Conference ユーザプレゼンテーション論文集
  
  Pages: 9-16
- Data Source
  KAKENHI-PROJECT-16560303
[Journal Article] 配線共有型マルチコンテキスト手法を用いた低消費電力化2006
- Author(s)
  門司秀明, 篠原拓, 飯田全広, 末吉敏則
- Journal Title
  
  電子情報通信学会技術研究報告 RECONF2006-50 106・394
  
  Pages: 67-42
- NAID
  110005716983
- Data Source
  KAKENHI-PROJECT-18300015
[Journal Article] FPGAのチップ面積および遅延を最適化するクラスタリング手法2006
- Author(s)
  木幡雅貴, 飯田全広, 末吉敏則
- Journal Title
  
  信学論 6(vol.J89-D)
  
  Pages: 1153-1162
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18300015
[Journal Article] Effective Clustering Technique to Optimize Routability of Outer Cluster Nets2006
- Author(s)
  Masaki Kobata, Masahiro Iida, Toshinori Sueyoshi
- Journal Title
  
  Fourteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays(FPGA2006)
  
  Pages: 229-229
- Data Source
  KAKENHI-PROJECT-16560303
[Journal Article] 粒度可変構造を持つ再構成可能論理セル向けテクノロジマッピング手法2006
- Author(s)
  中山英明, 山口良一, 尼崎太樹, 松山和憲, 飯田全広, 末吉敏則
- Journal Title
  
  電子情報通信学会技術研究報告 RECONF2006-55 106・394
  
  Pages: 67-72
- NAID
  110005716988
- Data Source
  KAKENHI-PROJECT-18300015
[Journal Article] Effective Clustering Technique to Optimize Routability of Outer Cluster Nets2006
- Author(s)
  Masaki Kobata, Masahiro Iida, Toshinori Sueyoshi
- Journal Title
  
  Proc. of Fourteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA2006)
  
  Pages: 229-229
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560303
[Journal Article] Adopting the Small-World Network in Routing Structure of FPGA2005
- Author(s)
  M.Iida, S.Abe, H.Tsukiashi, R.Ogata, T.Sueyoshi
- Journal Title
  
  Proc. of International Workshop on Applied Reconfiguradle Computing 2005 (ARC2005)
  
  Pages: 92-98
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560303
[Journal Article] Adopting the Small-World Network in Routing Structure of FPGA2005
- Author(s)
  M.Iida, S.Abe, H.Tsukiashi, R.Ogata, T.Sueyoshi
- Journal Title
  
  International Workshop on Applied Reconfigurable Computing 2005 (ARC2005)
  
  Pages: 92-98
- Data Source
  KAKENHI-PROJECT-16560303
[Journal Article] A low power design method using multi-context dynamic reconfiguration2005
- Author(s)
  Shigeki IMAI, Masahiro IIDA, Toshinori SUEYOSHI
- Journal Title
  
  Proc. of Commemorative International Technical Conference on Circuits/Systems, Computers and Communications 2
  
  Pages: 563-564
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560303
[Journal Article] RLDの動的再構成機能を利用した消費エネルギー削減手法2005
- Author(s)
  今井茂毅, 飯田全広, 末吉敏則
- Journal Title
  
  第12回FPGA/PLD Design Conferenceユーザ・プレゼンテーション講演論文集
  
  Pages: 57-64
- Data Source
  KAKENHI-PROJECT-16560303
[Journal Article] RLDの動的再構成機能を利用した消費エネルギー削減手法2005
- Author(s)
  今井茂毅, 飯田全広, 末吉敏則
- Journal Title
  
  第12回FPGA/PLD Design Conferenceユーザ・プレゼンテーション
  
  Pages: 57-64
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560303
[Journal Article] A low power design method using multi-context dynamic reconfiguration2005
- Author(s)
  Shigeki IMAI, Masahiro IIDA, Toshinori SUEYOSHI
- Journal Title
  
  Proc.of Commemorative International Technical Conference on Circuits/Systems, Computers and Communications Vol.2
  
  Pages: 563-564
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16560303
[Journal Article] Applying the Small-World Network to Routing Structure of FPGAs2005
- Author(s)
  Hisashi TSUKIASHI, Masahiro IIDA, Toshinori SUEYOSHI
- Journal Title
  
  Proc.of 15th International Conference on Field Programmable Logic and Applications (FPL2005)
  
  Pages: 65-70
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16560303
[Journal Article] Adopting the Small-World Network in Routing Structure of FPGA2005
- Author(s)
  M.Iida, S.Abe, H.Tsukiashi, R.Ogata, T.Sueyoshi
- Journal Title
  
  Proc.of International Workshop on Applied Reconfigurable Computing 2005 (ARC2005)
  
  Pages: 92-98
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16560303
[Journal Article] Development of a Run-Time Reconfigurable System using Partially Reconfigurable FPGA2005
- Author(s)
  Isao SAKAMOTO, Takanori SUSAKI, Hidetomo SHIBAMURA, Masahiro IIDA, Morihiro KUGA, Toshinori SUEYOSHI
- Journal Title
  
  Proc.of Commemorative International Technical Conference on Circuits/Systems, Computers and Communications Vol.2
  
  Pages: 599-600
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16560303
[Journal Article] 自律再構成による低消費エネルギー化手法2005
- Author(s)
  今井茂毅, 飯田全広, 末吉敏則
- Journal Title
  
  信学技法RECONF2005-44(2005-9) 105・288
  
  Pages: 19-24
- NAID
  110003494626
- Data Source
  KAKENHI-PROJECT-16560303
[Journal Article] A low power design method using multi-context dynamic reconfiguration2005
- Author(s)
  Shigeki IMAI, Masahiro IIDA, Toshinori SUEYOSHI
- Journal Title
  
  Proc. of The 20th Commemorative International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC2005) 2
  
  Pages: 563-564
- Data Source
  KAKENHI-PROJECT-16560303
[Journal Article] 動的再構成可能なデバイス向け低消費電力化手法の提案と評価2004
- Author(s)
  今井茂毅, 塚本和明, 飯田全広, 末吉敏則
- Journal Title
  
  情報処理学会 DAシンポジウム2004論文集 2004・8
  
  Pages: 145-150
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560303
[Journal Article] 次世代リコンフィギャラブル・ロジック向けクラスタリングツールの評価2004
- Author(s)
  木幡雅貴, 阿部晋也, 飯田全広, 末吉敏則
- Journal Title
  
  電子情報通信学会コンピュータシステム研究専門委員会所属第2種研究会第4回リコンフィギャラブルシステム研究会論文集
  
  Pages: 152-158
- Data Source
  KAKENHI-PROJECT-16560303
[Journal Article] RLDの動的再構成機能を積極的に利用した消費エネルギー削減手法2004
- Author(s)
  今井茂毅, 飯田全広, 末吉敏則
- Journal Title
  
  電子情報通信学会コンピュータシステム研究専門委員会所属第2種研究会第4回リコンフィギャラブルシステム研究会論文集
  
  Pages: 204-211
- Data Source
  KAKENHI-PROJECT-16560303
[Journal Article] 次世代リコンフィギャラブルロジック向けクラスタリングツールの開発2004
- Author(s)
  池田祐介, 木幡雅貴, 飯田全広, 末吉敏則
- Journal Title
  
  第17回回路とシステム軽井沢ワークショップ論文集
  
  Pages: 247-252
- Data Source
  KAKENHI-PROJECT-16560303
[Journal Article] 次世代リコンフィギャラブル・ロジック向けクラスタリングツールの開発2004
- Author(s)
  池田祐介, 木幡雅貴, 飯田全広, 末吉敏則
- Journal Title
  
  第17回回路とシステム軽井沢ワークショップ論文集
  
  Pages: 247-252
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560303
[Journal Article] 動的再構成可能なデバイス向け低消費電力化手法の提案と評価2004
- Author(s)
  今井茂毅, 塚本和明, 飯田全広, 末吉敏則
- Journal Title
  
  情報処理学会DAシンポジウム2004論文集 2004・8
  
  Pages: 145-150
- Data Source
  KAKENHI-PROJECT-16560303
[Patent] 演算装置、及び演算方法2019
- Inventor(s)
  飯田全広, 尼崎太樹, 古賀大顕
- Industrial Property Rights Holder
  飯田全広, 尼崎太樹, 古賀大顕
- Industrial Property Rights Type
  特許
- Industrial Property Number
  2019-211774
- Filing Date
  2019
- Data Source
  KAKENHI-PROJECT-17K00082
[Presentation] An FPGA design and implementation framework combined with commercial VLSI CADs2013
- Author(s)
  Qian Zhao, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  International Workshop on Reconfigurable Communication-centric Systems-on-Chip(ReCoSoC2013)
- Place of Presentation
  Darmstadt, Germany
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] An Automatic Design and Implementation Framework for Reconfigurable Logic IP Core2013
- Author(s)
  Qian Zhao, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  Proc. International Conference on ENGINEERING OF RECONFIGURABLE SYSTEMS AND ALGORITHMS (ERSA2013)
- Place of Presentation
  Las Vegas, Nevada, USA
- Year and Date
  2013-07-22
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] An Automatic Design and Implementation Framework for Reconfigurable Logic IP Core2013
- Author(s)
  Q.Zhao, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  Proc. of 23th International Conference on Field Programmable Logic and Applications (FPL2013)
- Place of Presentation
  Porto, Portugal
- Year and Date
  2013-09-04
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] A reconfigurable Java accelerator with software compatibility for embedded systems2013
- Author(s)
  Y.Ogawa, M.Iida, M.Amagasaki, M.Kuga and T.Sueyoshi
- Organizer
  International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies(HEART2013)
- Place of Presentation
  Edinburgh, Scotland
- Data Source
  KAKENHI-PROJECT-23650018
[Presentation] AN FPGA DESIGN AND IMPLEMENTATION FRAMEWORK COMBINED WITH COMMERCIAL VLSI CADS2013
- Author(s)
  Qian Zhao, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  Proc. 8th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC2013)
- Place of Presentation
  Darmstadt, Germany
- Year and Date
  2013-07-11
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] An Automatic Design and Implementation Framework for Reconfigurable Logic IP Core2013
- Author(s)
  Q.Zhao, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  23th International Conference on Field Programmable Logic and Applications (FPL2013)
- Place of Presentation
  Porto, Porutugal
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] A Novel FPGA Design Framework with VLSI Post-routing erformance Analysis2013
- Author(s)
  Q.Zhao, K.Inoue, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  Proc. 21st ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA2013)
- Place of Presentation
  Monterey, California
- Year and Date
  2013-02-12
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] DEFECT-ROBUST FPGA ARCHITECTURES FOR INTELLECTUAL PROPERTY CORES IN SYSTEM LSI2013
- Author(s)
  M.Amagasaki, Kazuki Inoue, Qian Zhao, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  23th International Conference on Field Programmable Logic and Applications (FPL2013)
- Place of Presentation
  Porto, Porutugal
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] DEFECT-ROBUST FPGA ARCHITECTURES FOR INTELLECTUAL PROPERTY CORES IN SYSTEM LSI2013
- Author(s)
  M.Amagasaki, Kazuki Inoue, Qian Zhao, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  Proc. of 23th International Conference on Field Programmable Logic and Applications (FPL2013)
- Place of Presentation
  Porto, Portugal
- Year and Date
  2013-09-02
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] An Automatic Design and Implementation Framework for Reconfigurable Logic IP Core2013
- Author(s)
  Qian Zhao, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  International Conference on ENGINEERING OF RECONFIGURABLE SYSTEMS AND ALGORITHMS(ERSA2013)
- Place of Presentation
  Las Vegas, Nevada, USA
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] Evaluation of fault tolerant technique based on homogeneous FPGA architecture2012
- Author(s)
  Y.Nishitani, K.Inoue, Motoki Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  Proc. the 20th IFIP International Conference on Very Large Scale Integration (VLSI-SoC2012)
- Place of Presentation
  Santa Cruz, USA
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] スケールフリーネットワークに基づくFPGA配線構造の基礎的検討2012
- Author(s)
  早馬悟司，尼崎太樹，飯田全広，久我守弘，末吉敏則
- Organizer
  信学技報 RECONF2012-50，vol.112，no.325，pp.17-22.
- Place of Presentation
  福岡市東区・九州大学
- Data Source
  KAKENHI-PROJECT-23650018
[Presentation] Accelerated evaluation of SEU failure-in-time using frame-based partial reconfiguration2012
- Author(s)
  Y.Ichinomiya, K.Takano, M.Amagasaki, M.Kuga, M.Iida and T.Sueyoshi
- Organizer
  Proc. International Conference on Field Programmable Technology(ICFPT2012)
- Place of Presentation
  Seoul, Korea
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] Designing flexible reconfigurable regions to relocate partial bitstreams2012
- Author(s)
  Y.Ichinomiya, S.Usagawa, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi,
- Organizer
  Proc. the 20th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM2012)
- Place of Presentation
  Toronto, Canada
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] A Novel Physical Defects Recovery Technique for FPGA-IP cores2012
- Author(s)
  Y.Nishitani, K.Inoue, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  Proc. International Conference on Reconfigurable Computing and FPGAs (ReConFig2012)
- Place of Presentation
  Cancun, Mexico
- Year and Date
  2012-12-06
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] Fault Detection and Avoidance of FPGA in Various Granularities2012
- Author(s)
  K.Inoue, Y.Nishitani, M.Amagasaki, M.Iida and T.Sueyoshi
- Organizer
  Proc. 22th International Conference on Field Programmable Logic and Applications (FPL2012)
- Place of Presentation
  Oslo, Norway
- Year and Date
  2012-08-29
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] Evaluation of fault tolerant technique based on homogeneous FPGA architecture2012
- Author(s)
  Y.Nishitani, K.Inoue, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  Proc. the 20th IFIP International Conference on Very Large Scale Integration
- Place of Presentation
  Santa Cruz, CA, USA
- Year and Date
  2012-10-10
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] 組込みシステムを対象としたリコンフィギャラブルJavaアクセラレータの一検討2012
- Author(s)
  高田誠也，尼崎太樹，飯田全広，久我守弘，末吉敏則
- Organizer
  信学技報 RECONF2012-48，vol.112，no.325，pp.9-14.
- Place of Presentation
  福岡市東区・九州大学
- Data Source
  KAKENHI-PROJECT-23650018
[Presentation] LUT間の入力共有に基づく小面積論理クラスク構造の一提案2011
- Author(s)
  高橋知也, 井上万輝, 尼崎太樹, 飯田全広, 久我守弘, 末吉敏則
- Organizer
  IEICEリコンフィギャラブルシステム研究会
- Place of Presentation
  名古屋大学
- Year and Date
  2011-09-26
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] Parallelization of the channel width search for FPGA routing2011
- Author(s)
  H.Sawada, M.Kuga, M.Amagasaki, M.Iida and T.Sueyoshi
- Organizer
  Second International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2011)
- Place of Presentation
  London, UK
- Data Source
  KAKENHI-PROJECT-23650018
[Presentation] An Easily Testable Routing Architecture of FPGA2011
- Author(s)
  M.Iida, K.Inoue, M.Amagasaki and T.Sueyoshi
- Organizer
  Proc. the 19th IFIP International Conference on Very Large Scale Integration (VLSI-SoC2011)
- Place of Presentation
  Hong Cong, China
- Year and Date
  2011-10-03
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] \AN EASILY TESTABLE ROUTING ARCHITECTURE AND EFFICIENT TEST TECHNIQUE2011
- Author(s)
  K.Inoue, H.Yosho, M.Amagasaki, M.Iida, T.Sueyoshi
- Organizer
  21th International Conference on Field Programmable Logic and Applications (FPL2011)
- Place of Presentation
  Chania, Greece
- Year and Date
  2011-09-06
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] AN EASILY TESTABLE ROUTING ARCHITECTURE AND EFFICIENT TEST TECHNIQUE2011
- Author(s)
  K.Inoue, H.Yosho, M.Amagasaki, M.Iida and T.Sueyoshi
- Organizer
  Proc. 21th International Conference on Field Programmable Logic and Applications (FPL2011)
- Place of Presentation
  Chania, Greece
- Year and Date
  2011-09-06
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] ホモジニアスな配線構造によるFPGA設計の容易化2011
- Author(s)
  井上万輝, 尼崎太樹, 飯田全広
- Organizer
  IEICEリコンフィギャラブルシステム研究会
- Place of Presentation
  北海道大学
- Year and Date
  2011-05-13
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] An Easily Testable Routing Architecture of FPGA2011
- Author(s)
  M.Iida, K.Inoue, M.Amagasaki, T.Sueyoshi
- Organizer
  19th IFIP International Conference on Very Large Scale Integration (VLSI-SoC2011)
- Place of Presentation
  Hong Cong, Chaina
- Year and Date
  2011-10-03
- Data Source
  KAKENHI-PROJECT-23300017

1. SUEYOSHI Toshinori (00117136)

# of Collaborated Projects: 2 results

# of Collaborated Products: 39 results
2. AMAGASAKI Motoki (50467974)

# of Collaborated Projects: 2 results

# of Collaborated Products: 30 results

IIDA MASAHIRO 飯田 全広

飯田 全広 イイダ マサヒロ

IIDA Masahiro 飯田 全広

Research Projects

Research Products

Co-Researchers

A study of SNN device using serial approximate addersPrincipal Investigator

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Review Section

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A study on low delay network topology for a large scale parallel computing systemPrincipal Investigator

Principal Investigator

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A Study of High Dependability Reconfigurable Logic ArchitecturePrincipal Investigator

Principal Investigator

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Research on programming model for Reconfigurable SystemsPrincipal Investigator

Principal Investigator

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A study of the integrated EDA tools for reconfigurable logicPrincipal Investigator

Principal Investigator

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A LOW ENERGY DESIGN METHOD USING MULTI-CONTEXT RECONFIGURATIONPrincipal Investigator

Principal Investigator

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Research Institution

[Journal Article] LSI化の検討に使用するSNNシミュレータSULIの開発と評価2023

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[Journal Article] Order Adjustment Approach Using Cayley Graphs for the Order/Degree Problem2018

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[Journal Article] FPGAを用いたグラフストリーム処理の一検討2017

Author(s)

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Data Source

[Journal Article] A reconfigurable Java accelerator with software compatibility for embedded systems2013

Author(s)

Journal Title

Data Source

[Journal Article] システムLSI搭載FPGA-IPコア向け物理故障検出及び回避手法2013

Author(s)

Journal Title

NAID

Data Source

[Journal Article] システムLSI搭載FPGA-IPコア向け物理故障検出及び回避手法2013

Author(s)

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NAID

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[Journal Article] 仮想CGRAへのJavaソフトウェアのマッピングとFPGA実装2013

Author(s)

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[Journal Article] FPGA Design Framework Combined with Commercial VLSI CAD2013

Author(s)

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IIDA MASAHIRO 飯田全広

飯田全広イイダマサヒロ

IIDA Masahiro 飯田全広