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Takagi Naofumi  高木 直史

ORCIDConnect your ORCID iD *help
… Alternative Names

TAKAGI Naofumi  高木 直史

NAOFUMI Takagi  高木 直史

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Researcher Number 10171422
Other IDs
External Links
Affiliation (Current) 2025: 金沢学院大学, 情報工学部, 教授
Affiliation (based on the past Project Information) *help 2016 – 2023: 京都大学, 情報学研究科, 教授
2012 – 2014: 京都大学, 情報学研究科, 教授
2010: 京都大学, 大学院・情報学研究科, 教授
2010: Nagoya University, 大学院・情報学研究科, 教授
2007 – 2009: Nagoya University, 大学院・情報科学研究科, 教授 … More
2006: 名古屋大学, 大学院情報科学研究科, 教授
2004 – 2005: Nagoya University, Graduate School of Information Science, Professor, 大学院・情報科学研究科, 教授
2003: 名古屋大学, 情報科学研究科, 教授
2002: 名古屋大学, 工学研究科, 教授
1998 – 2000: 名古屋大学, 工学研究科, 教授
1997: 名古屋大学, 大学院・工学研究科, 助教授
1997: Nagoya University, Graduate school of Engineering, Associete Professor, 工学研究科, 助教授
1994 – 1996: Nagoya University, Faculty of Engineering, Assoc.Professor, 工学部, 助教授
1991 – 1993: Kyoto University, Faculty of Engineering, Assoc. Professor, 工学部, 助教授
1986 – 1990: Faculty of Engineering,Kyoto University, 工学部, 助手 Less
Review Section/Research Field
Principal Investigator
計算機科学 / Computer system/Network / Computer system / Science and Engineering
Except Principal Investigator
計算機工学 / 計算機科学 / 情報工学 / Science and Engineering / Science and Engineering
Keywords
Principal Investigator
VLSI / ハードウェアアルゴリズム / 算術演算回路 / 剰余除算 / 計算複雑さ / hardware algorithm / べき乗算 / 乗算 / 算術演算 / アルゴリズム … More / 剰余系演算 / 乗算器 / 正弦・余弦関数計算 / 指数・対数関数計算 / FPGA / 逆三角関数 / FPGA / 浮動小数点演算 / 関数計算 / 計算機システム / cryptosystem / modular reduction / integer Division / modular arithmetic / finite field arithmetic / 暗号化・復号 / 有限体上の除算 / 剰余系除算 / 乗算剰余算 / 暗号処理 / 剰余計算 / 整数除算 / 有限体上の演算 / modular division / division in GF (2^m) / powering / cube rooting / Euclidean norm computation / arithmetic circuit / 加算木 / 加算 / 三角関数計算 / 復号 / 符号化 / コンピュータグラフィクス / ノルム計算 / GF(2^m)上の除算 / 立方根計算 / ユークリッドノルム計算 / ハート・ウェアアルゴリズム / Hardware algorithm / Modular division / Powering / Multiply-addition / Square rooting / Division / Multiplication / Computer arithmetic / ディジタル信号処理 / べき乗計算 / 積和演算 / 開平 / 除算 / (2)算術演算回路 / オンライン誤り検出 / 演算器アレイ / テスト容易化設計 / 加算器 / VLSIのテスト / 組合せ回路 / 剰余べき乗算 / 剰余乗算 / 線形配置問題 / レイアウト / 剰余逆数計算 / 冗長表現 / 論理回路設計 … More
Except Principal Investigator
論理設計検証 / 時相論理 / Binary Decision Diagram / 論理関数処理 / 二分決定グラフ / Logic Simulation / Logic Design Verification / Logic Design / Temporal Logic / 記号シミュレ-ション / 仕様記述 / 論理設計 / タイミング検証 / 論理設計支援 / 論理シミュレーション / Hardware Algorithm / 算術演算回路 / ハードウェアアルゴリズム / 順序回路 / Boolean Function Manipulation / Boolean Function / 計算複雑さ / 論理関数 / Symbolic Simulation / Timing Verification / 論理シミュレ-ション / Model Checking / Formal Verification / 形式的検証 / 単一磁束量子回路 / 超伝導回路 / 磁束量子回路 / パルス駆動回路 / パルス論理 / 半磁束量子回路 / π接合 / 量子化条件 / マトリクスメモリ / 磁性ジョセフソン接合 / 半磁束量子 / 単一磁束量子 / Redundant Coding / Test Generation / Fault Simulation / On-Line Error Detection / Fault-Tolerant Design / Arithmetic Circuits / 故障シミュレーション / 冗長符号化 / テスト生成 / 故障シミュレ-ション / オンライン誤り検出 / 耐故障設計 / ハ-ドウェアアルゴリズム / Workstation / Specification Desctiption / Vector Processof / 代数的仕様記述 / 正則時相論理 / 高水準ハードウェア記述 / 論理シミュレータ / マルチスクリーン / ワークステーション / ベクトルプロセッサ / Unification / Residue Number Representation / Arithmetic Operation / VLSI; Redundant Binary Representation / Redundant Representation / ハードウェア設計言語 / 単一化操作 / 剰余数表示法 / 冗長2進表現 / 超LSI / 冗長表現 / Formal Specification / Logic Function Manipulation / 形式的論理設計検証 / 論理開数処理 / モデルチェッキング / Combinatorial Problem / Content Addressable Memory / Computational Complexity / Prallel Algorithm / Computer Aided Logic Design / 形式的設計検証 / 組合せ問題 / 内容アドレスメモリ / 並列アルゴリズム / computer-aided logic design / temporal logic / state assignment / logic function optimization / sequential circuits / logic design verification / logic synthesis / 状態割当て / 論理関数簡単化 / 論理合成 / Computational complexity / computer Aided Design / 計算機援用設計 / Hazard / Asynchronous Sequential Circuit / 論立設計検証 / ハザ-ド / 非同期式順序回路 / 共有二分決定グラフ / 順序機械 / 正則集合 / 設計検証 / モデル検査 / 単一磁束量子論理回路 / クロック配信 / 局在電磁波配線 Less
  • Research Projects

    (21 results)
  • Research Products

    (117 results)
  • Co-Researchers

    (18 People)
  •  Research on ultra-low power sub-terahertz superconducting quantum digital systems based on pulse-driven circuits

    • Principal Investigator
      Fujimaki Akira
    • Project Period (FY)
      2018 – 2022
    • Research Category
      Grant-in-Aid for Specially Promoted Research
    • Review Section
      Science and Engineering
    • Research Institution
      Nagoya University
  •  Studies on hardware assist of floating point function calculationPrincipal Investigator

    • Principal Investigator
      Takagi Naofumi
    • Project Period (FY)
      2016 – 2019
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      Computer system
    • Research Institution
      Kyoto University
  •  Research on high-performance and highly-dependable floating-point arithmetic unit arrays by contriving data representationPrincipal Investigator

    • Principal Investigator
      TAKAGI Naofumi
    • Project Period (FY)
      2012 – 2014
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      Computer system/Network
    • Research Institution
      Kyoto University
  •  Research on synthesis of easily-testable arithmetic circuitsPrincipal Investigator

    • Principal Investigator
      TAKAGI Naofumi
    • Project Period (FY)
      2008 – 2010
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      Computer system/Network
    • Research Institution
      Nagoya University
  •  Studies on Logic Design and Design Automation of Single-Flux-Quantum Circuits based on Localized Electromagnetic Waves

    • Principal Investigator
      KAZUYOSHI Takagi (TAKAGI Kazuyoshi)
    • Project Period (FY)
      2006 – 2009
    • Research Category
      Grant-in-Aid for Scientific Research on Priority Areas
    • Review Section
      Science and Engineering
    • Research Institution
      Nagoya University
  •  ハードウェアアルゴリズムの性能評価に関する研究Principal Investigator

    • Principal Investigator
      高木 直史
    • Project Period (FY)
      2004 – 2007
    • Research Category
      Grant-in-Aid for Scientific Research on Priority Areas
    • Review Section
      Science and Engineering
    • Research Institution
      Nagoya University
  •  Researches on hardware algorithms for arithmetic operations in finite fields.Principal Investigator

    • Principal Investigator
      TAKAGI Naofumi
    • Project Period (FY)
      2002 – 2004
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      計算機科学
    • Research Institution
      Nagoya University
  •  Studies on hardware algorithms for high-performance arithmetic circuitsPrincipal Investigator

    • Principal Investigator
      TAKAGI Naofumi
    • Project Period (FY)
      1998 – 2000
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      計算機科学
    • Research Institution
      Nagoya University
  •  Studies on combined arithmetic circuits for high-speed digital signal processingPrincipal Investigator

    • Principal Investigator
      TAKAGI Naofumi
    • Project Period (FY)
      1996 – 1997
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      計算機科学
    • Research Institution
      Nagoya University
  •  剰余系演算用高速アルゴリズムに関する研究Principal Investigator

    • Principal Investigator
      高木 直史
    • Project Period (FY)
      1995
    • Research Category
      Grant-in-Aid for Encouragement of Young Scientists (A)
    • Research Field
      計算機科学
    • Research Institution
      Nagoya University
  •  論理回路のレイアウト複雑さに関する研究Principal Investigator

    • Principal Investigator
      高木 直史
    • Project Period (FY)
      1994
    • Research Category
      Grant-in-Aid for Encouragement of Young Scientists (A)
    • Research Field
      計算機科学
    • Research Institution
      Nagoya University
  •  冗長表現を用いた高速演算回路の自動合成に関する研究Principal Investigator

    • Principal Investigator
      高木 直史
    • Project Period (FY)
      1993
    • Research Category
      Grant-in-Aid for Encouragement of Young Scientists (A)
    • Research Field
      計算機科学
    • Research Institution
      Kyoto University
  •  Basic Research on High-Speed Boolean Function Manipulator

    • Principal Investigator
      YAJIMA Shuzo
    • Project Period (FY)
      1993 – 1994
    • Research Category
      Grant-in-Aid for General Scientific Research (B)
    • Research Field
      計算機科学
    • Research Institution
      KYOTO UNIVERSITY
  •  Research on Formal Verifier of Logic Design Based on Temporal Logic

    • Principal Investigator
      YAJIMA Shuzo
    • Project Period (FY)
      1993 – 1994
    • Research Category
      Grant-in-Aid for Developmental Scientific Research (B)
    • Research Field
      計算機科学
    • Research Institution
      KYOTO UNIVERSITY
  •  Research on Development of Logic Synthesizer and Design Verifier for Sequential Circuits Based on Boolean Function Manipulation

    • Principal Investigator
      YAJIMA Shuzo
    • Project Period (FY)
      1991 – 1992
    • Research Category
      Grant-in-Aid for Developmental Scientific Research (B)
    • Research Field
      情報工学
    • Research Institution
      KYOTO UNIVERSITY
  •  Research on Efficient Manipulation of Boolean Functions Using Shared Binary Decision Diagrams and Its Application to Computer Aided Logic Design

    • Principal Investigator
      YAJIMA Shuzo
    • Project Period (FY)
      1990 – 1991
    • Research Category
      Grant-in-Aid for General Scientific Research (B)
    • Research Field
      情報工学
    • Research Institution
      Kyoto University
  •  Researches on Formal Logic Design Verification Based on Regular Temporal Logic

    • Principal Investigator
      HIRAISHI Hiromi
    • Project Period (FY)
      1989 – 1990
    • Research Category
      Grant-in-Aid for General Scientific Research (C)
    • Research Field
      計算機工学
    • Research Institution
      Kyoto University
  •  Research on Development of a Logic Design Verification System Based on Time-Symbolic Simulation

    • Principal Investigator
      YAJIMA Shuzo
    • Project Period (FY)
      1989 – 1990
    • Research Category
      Grant-in-Aid for Developmental Scientific Research (B).
    • Research Field
      計算機工学
    • Research Institution
      Kyoto University
  •  Researches on the Design of Highly Reliable High-Speed Arithmetic Circuits with Redundant Coding

    • Principal Investigator
      YAJIMA Shuzo
    • Project Period (FY)
      1988 – 1989
    • Research Category
      Grant-in-Aid for General Scientific Research (B)
    • Research Field
      計算機工学
    • Research Institution
      KYOTO UNIVERSITY
  •  Research on Development of High-Speed Logic Simulators Using a Vector Processor and Logic Design Verification Systems

    • Principal Investigator
      YAJIMA Shuzo
    • Project Period (FY)
      1986 – 1987
    • Research Category
      Grant-in-Aid for Developmental Scientific Research
    • Research Field
      計算機工学
    • Research Institution
      Kyoto University
  •  Research on Design of VLSI Oriented Hardware Algorithms Using Redundant Representation

    • Principal Investigator
      YAJIMA Shuzo
    • Project Period (FY)
      1985 – 1986
    • Research Category
      Grant-in-Aid for General Scientific Research (B)
    • Research Field
      計算機工学
    • Research Institution
      Kyoto University

All 2023 2022 2021 2020 2019 2018 2017 2014 2013 2012 2010 2009 2008 2007 2006 2005 2004 2003 2002 Other

All Journal Article Presentation Patent

  • [Journal Article] Wire Length-Matching Aware Placement Method for Rapid Single Flux Quantum Logic Circuits2023

    • Author(s)
      Kitamura Kento、Kawaguchi Takahiro、Takagi Naofumi
    • Journal Title

      IEEE Transactions on Applied Superconductivity

      Volume: 33 Issue: 5 Pages: 1-5

    • DOI

      10.1109/tasc.2023.3262216

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18H05211
  • [Journal Article] Technology Mapping With Clockless Gates for Logic Stage Reduction of RSFQ Logic Circuits2023

    • Author(s)
      Kito Nobutaka、Kawaguchi Takahiro、Takagi Kazuyoshi、Takagi Naofumi
    • Journal Title

      IEEE Transactions on Applied Superconductivity

      Volume: 33 Issue: 5 Pages: 1-5

    • DOI

      10.1109/tasc.2023.3245049

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22K11961, KAKENHI-PROJECT-18H05211
  • [Journal Article] Logic-Depth-Aware Technology Mapping Method for RSFQ Logic Circuits With Special RSFQ Gates2022

    • Author(s)
      KITO, Nobutaka、TAKAGI, Kazuyoshi、TAKAGI, Naofumi
    • Journal Title

      IEEE Transactions on Applied Superconductivity

      Volume: 32 Issue: 4 Pages: 1-5

    • DOI

      10.1109/tasc.2021.3129719

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-19K11888, KAKENHI-PROJECT-18H05211
  • [Journal Article] 32-Bit ALU with Clockless Gates for RSFQ Bit-Parallel Processor2022

    • Author(s)
      Kawaguchi Takahiro、Takagi Naofumi
    • Journal Title

      IEICE Trans. Electron.

      Volume: E105.C Issue: 6 Pages: 245-250

    • DOI

      10.1587/transele.2021SEP0005

    • NAID

      130008124492

    • ISSN
      0916-8524, 1745-1353
    • Year and Date
      2022-06-01
    • Language
      English
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18H05211
  • [Journal Article] Static Timing Analysis for Single-Flux-Quantum Circuits Composed of Various Gates2022

    • Author(s)
      Kawaguchi Takahiro、Takagi Kazuyoshi、Takagi Naofumi
    • Journal Title

      IEEE Transactions on Applied Superconductivity

      Volume: 32 Issue: 5 Pages: 1-9

    • DOI

      10.1109/tasc.2022.3161052

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18H05211
  • [Journal Article] A Timing Fault Model and an Efficient Timing Fault Simulation Method for Rapid Single-Flux-Quantum Logic Circuits2021

    • Author(s)
      NAKAMURA, Shogo、TAKAGI, Kazuyoshi、KITO, Nobutaka、TAKAGI, Naofumi
    • Journal Title

      Journal of Physics: Conference Series

      Volume: 1975 Issue: 1 Pages: 012026-012026

    • DOI

      10.1088/1742-6596/1975/1/012026

    • Peer Reviewed / Open Access / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-19K11888, KAKENHI-PROJECT-18H05211
  • [Journal Article] Rapid Single-Flux-Quantum Logic Circuits Using Clockless Gates2021

    • Author(s)
      Kawaguchi Takahiro、Takagi Kazuyoshi、Takagi Naofumi
    • Journal Title

      IEEE Transactions on Applied Superconductivity

      Volume: 31 Issue: 4 Pages: 1-7

    • DOI

      10.1109/tasc.2021.3068960

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18H05211
  • [Journal Article] Conversion Method of Netlists Consisting of Conventional Logic Gates to RSFQ Logic Circuits Utilizing Special RSFQ Gates2020

    • Author(s)
      Kito Nobutaka、Takagi Kazuyoshi、Takagi Naofumi
    • Journal Title

      IEEE Transactions on Applied Superconductivity

      Volume: 30 Issue: 7 Pages: 1-6

    • DOI

      10.1109/tasc.2020.3012474

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-19K11888, KAKENHI-PROJECT-18H05211
  • [Journal Article] Layout Design Flow for RSFQ Circuits Based on Cell Clustering and Mixed Wiring of JTLs and PTLs2020

    • Author(s)
      Takashi Dejima, Kazuyoshi Takagi, and Naofumi Takagi
    • Journal Title

      IEEE Transactions on Applied Superconductivity

      Volume: 30-7 Issue: 7 Pages: 1302506-1302506

    • DOI

      10.1109/tasc.2020.3014928

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18H05211, KAKENHI-PROJECT-18K11213
  • [Journal Article] A Two-Step Routing Method with Wire Length Budgeting for PTL Routing of SFQ Logic Circuits2020

    • Author(s)
      Kei Kitamura, Kazuyoshi Takagi, and Naofumi Takagi
    • Journal Title

      Journal of Physics

      Volume: 1590 Issue: 1 Pages: 012043-012043

    • DOI

      10.1088/1742-6596/1590/1/012043

    • Peer Reviewed / Open Access
    • Data Source
      KAKENHI-PROJECT-18H05211, KAKENHI-PROJECT-18K11213
  • [Journal Article] Concurrent Error Detectable Carry Select Adder with Easy Testability2019

    • Author(s)
      Nobutaka Kito, Naofumi Takagi
    • Journal Title

      IEEE Transactions on Computers

      Volume: 68 Issue: 7 Pages: 1105-1110

    • DOI

      10.1109/tc.2019.2895074

    • Peer Reviewed / Open Access
    • Data Source
      KAKENHI-PROJECT-16H02795
  • [Journal Article] Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis2014

    • Author(s)
      Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
    • Journal Title

      IEICE Trans. Fundamentals

      Volume: E97.A Issue: 12 Pages: 2498-2506

    • DOI

      10.1587/transfun.E97.A.2498

    • NAID

      130004706413

    • ISSN
      0916-8508, 1745-1337
    • Language
      English
    • Peer Reviewed / Acknowledgement Compliant
    • Data Source
      KAKENHI-PROJECT-24300019, KAKENHI-PROJECT-26870303
  • [Journal Article] Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication2013

    • Author(s)
      Nobutaka Kito, Naofumi Takagi
    • Journal Title

      IEICE Trans. Inf. & Syst.

      Volume: E96.D Issue: 9 Pages: 1962-1970

    • DOI

      10.1587/transinf.E96.D.1962

    • NAID

      130003370984

    • ISSN
      0916-8532, 1745-1361
    • Language
      English
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-24300019, KAKENHI-PROJECT-25730033
  • [Journal Article] A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier2010

    • Author(s)
      Nobutaka Kito, Kensuke Hanai, Naofumi Takagi
    • Journal Title

      IEICE Trans.on Information and Systems

      Volume: E93-D Pages: 2783-2791

    • NAID

      10027641210

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-20300016
  • [Journal Article] A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier2010

    • Author(s)
      Nobutaka Kito、Kensuke Hanai、Naofumi Takagi
    • Journal Title

      IEICE Transactions on Information and Systems vol.E93-D、no.10

      Pages: 2783-2791

    • NAID

      10027641210

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-20300016
  • [Journal Article] けた上げ保存加算器で構成された部分積加算部をもつ乗算器のテスト2009

    • Author(s)
      鬼頭信貴、高木直史
    • Journal Title

      電子情報通信学会論文誌D J92-D巻、7号

      Pages: 994-1002

    • NAID

      110007331954

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-20300016
  • [Journal Article] Bipartite modular multiplication method2008

    • Author(s)
      M. E. Kaihara and N. Takagi
    • Journal Title

      IEEE Transactions on Computers Vol. 57, No. 2

      Pages: 157-164

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-16092210
  • [Journal Article] A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits2008

    • Author(s)
      Koji Obata, Kazuyoshi Takagi, Naofumi Takagi
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E91-A

      Pages: 3772-3782

    • NAID

      10026854486

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18080008
  • [Journal Article] A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits2008

    • Author(s)
      Koji Obata, Kazuyoshi Takagi, Naofumi Takagi
    • Journal Title

      IEICE Trans. Fundamentals Vol.E91-A

      Pages: 3772-3782

    • NAID

      10026854486

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18080008
  • [Journal Article] 種々の部分積加算構造をもつテスト容易な乗算器の設計手法2008

    • Author(s)
      鬼頭信貴、高木直史
    • Journal Title

      電子情報通信学会論文誌D J91-D巻、10号

      Pages: 2478-2486

    • NAID

      110007380919

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-20300016
  • [Journal Article] A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits2008

    • Author(s)
      Koji Obata, Kazuyoshi Takagi, Naofumi Takagi
    • Journal Title

      IEICE Trans. Fundamentals E91-A

      Pages: 3772-3782

    • NAID

      10026854486

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18080008
  • [Journal Article] 種々の部分積加算構造をもっテスト容易な乗算器の設計手法2008

    • Author(s)
      鬼頭信貴, 高木直史
    • Journal Title

      電子情報通信学会論文誌D J91-D, No. 10

      Pages: 2478-2486

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-20300016
  • [Journal Article] A method of sequential circuit synthesis using one-hot encoding for single-flux-quantum digital circuits2007

    • Author(s)
      Koji Obata, Kazuyoshi Takagi, Naofumi Takagi
    • Journal Title

      IEICE Trans. Electron. E90-C

      Pages: 2278-2284

    • NAID

      110007538875

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18080008
  • [Journal Article] A method of sequential circuit synthesis using one-hot encoding for sing le-flux-quantum digital circuits2007

    • Author(s)
      K. Obata, K. Takagi, N. Takagi
    • Journal Title

      IEICE Trans. Electron. E90-C

      Pages: 2278-2284

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18080008
  • [Journal Article] 拡張ユークリッド法に基づくGF(2m)上の乗算・逆元計算のための複合回路2007

    • Author(s)
      小林克希, 高木直史
    • Journal Title

      電子情報通信学会技術研究報告 VLD2006-142

      Pages: 13-18

    • NAID

      110006248801

    • Data Source
      KAKENHI-PROJECT-16092210
  • [Journal Article] An algorithm for inversion in GF(2^m)suitable for implementation using a polynomial multiply instruction on GF(2)2007

    • Author(s)
      K. Kobayashi, N. Takagi and K. Takagi
    • Journal Title

      Proc. of the 18th IEEE Symposium on Computer Arithmetic

      Pages: 105-112

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-16092210
  • [Journal Article] 配線層数の乗算器の回路面積への影響について2007

    • Author(s)
      川島裕崇, 高木直史, 高木一義
    • Journal Title

      電子情報通信学会技術研究報告 VLD2006-141

      Pages: 7-12

    • NAID

      110006248800

    • Data Source
      KAKENHI-PROJECT-16092210
  • [Journal Article] Design of a combined circuit for multiplication and inversion in GF(2^m)2007

    • Author(s)
      K. Kobayashi and N. Takagi
    • Journal Title

      Proc. of the Workshop on Synthesis and System Integration of Mixed Information Technologies 2007

      Pages: 15-20

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-16092210
  • [Journal Article] A Method of Sequential Circuit Synthesis using One-hot Encoding for Single-Flux-Quantum Digital Circuits2007

    • Author(s)
      Koji Obata, Kazuyoshi Takagi, Naofumi Takagi
    • Journal Title

      IEICE Trans. Electron. Vol.E90-C

      Pages: 2278-2284

    • NAID

      110007538875

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18080008
  • [Journal Article] Hardware algorithm for computing reciprocal of Euclidean norm of a 3-D vector2006

    • Author(s)
      F.Kumazawa, N.Takagi
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A, 6

      Pages: 1799-1806

    • NAID

      110007502924

    • Data Source
      KAKENHI-PROJECT-16092210
  • [Journal Article] A hardware algorithm for integer division using the SD2 representation2006

    • Author(s)
      N.Takagi, S.Kadowaki, K Takagi
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A, 10

      Pages: 2874-2881

    • NAID

      110007537767

    • Data Source
      KAKENHI-PROJECT-16092210
  • [Journal Article] A VLSI algorithm for integer square-rooting2006

    • Author(s)
      N.Takagi, K Takagi
    • Journal Title

      Proc. 2006 International Symposium on Intelligent Signal Processing and Communication Systems

      Pages: 626-629

    • Data Source
      KAKENHI-PROJECT-16092210
  • [Journal Article] Pipelined bipartite modular multiplication2005

    • Author(s)
      M.E.Kaihara, N.Takagi
    • Journal Title

      電子情報通信学会技術研究報告 VLD2005-67

      Pages: 37-42

    • NAID

      110004018526

    • Data Source
      KAKENHI-PROJECT-16092210
  • [Journal Article] A hardware algorithm for integer division2005

    • Author(s)
      N.Takagi, S.Kadowaki, K.Takagi
    • Journal Title

      Proceedings of the 17th IEEE Symposium on Computer Arithmetic

      Pages: 140-146

    • Data Source
      KAKENHI-PROJECT-16092210
  • [Journal Article] Karatsubaアルゴリズムに基づく小面積並列乗算器2005

    • Author(s)
      柴岡雅之, 高木直史, 高木一義
    • Journal Title

      2005年電子情報通信学会総合大会講演論文集 基礎・境界

    • NAID

      110004737800

    • Data Source
      KAKENHI-PROJECT-16092210
  • [Journal Article] Hardware algorithm for modular multiplication/division based on the extended Euclidean algorithm2005

    • Author(s)
      M.E.Kaihara, N.Takagi
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A,12

      Pages: 3610-3617

    • NAID

      110004019470

    • Data Source
      KAKENHI-PROJECT-16092210
  • [Journal Article] A hardware algorithm for modular multiplication/division2005

    • Author(s)
      M.E.Kaihara, N.Takagi
    • Journal Title

      IEEE Transactions on Computers Vol.54, no.1

      Pages: 12-21

    • NAID

      120000978657

    • Data Source
      KAKENHI-PROJECT-14380142
  • [Journal Article] A hardware algorithm for integer division2005

    • Author(s)
      N.Takagi, S.Kadowaki
    • Journal Title

      Proc.of 17th IEEE Symposium on Computer Arithmetic (発表予定)

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-14380142
  • [Journal Article] 算術演算のための減算シフト型ハードウェアアルゴリズムの自動合成ツールの構築2005

    • Author(s)
      熊澤文雄, 高木直史
    • Journal Title

      情報処理学会「DAシンポジウム2005」論文集

      Pages: 213-236

    • Data Source
      KAKENHI-PROJECT-16092210
  • [Journal Article] A hardware algorithm for modular multiplication/division2005

    • Author(s)
      M.E.Kaihara, N.Takagi
    • Journal Title

      IEEE Transactions on Computers Vol.54,no.1

      Pages: 12-21

    • NAID

      120000978657

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-14380142
  • [Journal Article] A hardware algorithm for integer division2005

    • Author(s)
      N.Takagi, S.Kadowaki
    • Journal Title

      Proc.of 17th IEEE Symposium on Computer Arithmetic (発表予定)

    • Data Source
      KAKENHI-PROJECT-16092210
  • [Journal Article] A hardware algorithm for modular multiplication/division2005

    • Author(s)
      M.E.Kaihara, N.Takagi
    • Journal Title

      IEEE Trans.Computers vol.54, no.1

      Pages: 12-21

    • NAID

      120000978657

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-14380142
  • [Journal Article] Bipartite modular multiplication2005

    • Author(s)
      M.E.Kaihara, N.Takagi
    • Journal Title

      Springer LNCS3659: Proceedings of 7th International Workshop on Cryptographic Hardware and Embedded Systems -CHES 2005

      Pages: 201-210

    • NAID

      120000982145

    • Data Source
      KAKENHI-PROJECT-16092210
  • [Journal Article] A hardware algorithm for integer division2005

    • Author(s)
      N.Takagi, S.Kadowaki
    • Journal Title

      Proc.17th IEEE Symp.on Computer Arithmetic (to appear)

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-14380142
  • [Journal Article] 算術演算のための減算シフト型ハードウェアアルゴリズムの自動合成2004

    • Author(s)
      熊澤文雄, 高木直史
    • Journal Title

      電子情報通信学会技術研究報告 VLD2004-90

      Pages: 175-178

    • NAID

      110003318205

    • Data Source
      KAKENHI-PROJECT-16092210
  • [Journal Article] A multiplier/divider for modular arithmetic based on the extended Euclidean algorithm2004

    • Author(s)
      M.E.Kaihara, N.Takagi
    • Journal Title

      IEICE Technical Report VLD2004-1

      Pages: 1-6

    • NAID

      110003294338

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-14380142
  • [Journal Article] GF(2^m)上の逆元算出のための拡張ユークリッド法に基づくテーブルを用いたアルゴリズム2004

    • Author(s)
      小林克希, 高木直史, 高木一義
    • Journal Title

      電子情報通信学会技術研究報告 VLD2004-2

      Pages: 7-12

    • NAID

      110003294339

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-14380142
  • [Journal Article] 冗長2進表現の絶対値計算を用いた整数除算回路2004

    • Author(s)
      門脇俊介, 高木直史, 高木一義
    • Journal Title

      電子情報通信学会技術研究報告 VLD2004-3

      Pages: 13-18

    • Data Source
      KAKENHI-PROJECT-14380142
  • [Journal Article] An algorithm using look-up table based on extended Euclid's algorithm for computing inversion in GF(2^m)2004

    • Author(s)
      K.Kobayashi, N.Takagi, K.Takagi
    • Journal Title

      IEICE Technical Report VLD2004-2

      Pages: 7-12

    • NAID

      110003294339

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-14380142
  • [Journal Article] 拡張ユークリッド法に基づく剰余系乗除算回路2004

    • Author(s)
      カイハラ マルセロ, 高木直史
    • Journal Title

      電子情報通信学会技術研究報告 VLD2004-1

      Pages: 1-6

    • NAID

      110003294338

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-14380142
  • [Journal Article] A VLSI algorithm for modular multiplication/division2003

    • Author(s)
      M.E.Kaihara, N.Takagi
    • Journal Title

      Proc.16th IEEE Symp.on Computer Arithmetic

      Pages: 220-227

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-14380142
  • [Journal Article] A VLSI algorithm for modular multiplication/division2003

    • Author(s)
      M.E.Kaihara, N.Takagi
    • Journal Title

      Proc.of 16th IEEE Symposium on Computer Arithmetic

      Pages: 220-227

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-14380142
  • [Journal Article] A VLSI algorithm for division in GF(2^m) based on extended binary GCD algorithm2002

    • Author(s)
      Y.Watanabe, N.Takagi, K.Takagi
    • Journal Title

      IEICE Transactions on Fundamentals vol.E85-A, no.5

      Pages: 994-999

    • NAID

      110003209115

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-14380142
  • [Journal Article] A VLSI algorithm for division in GF(2m) based on extended binary GCD algorithm2002

    • Author(s)
      Y.Watanabe, N.Takagi, K.Takagi
    • Journal Title

      IEICE Trans.Fundamentals vol.E85-A, no.5

      Pages: 994-999

    • NAID

      110003209115

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-14380142
  • [Patent] 剰余系の計算方法及び装置2006

    • Inventor(s)
      高木 直史, カイハラ マルセロ
    • Industrial Property Rights Holder
      名古屋大学
    • Industrial Property Number
      2006-040859
    • Filing Date
      2006-02-17
    • Data Source
      KAKENHI-PROJECT-16092210
  • [Patent] 剰余系の計算方法及び装置並びにプログラム2005

    • Inventor(s)
      高木 直史, カイハラ マルセロ
    • Industrial Property Rights Holder
      名古屋大学
    • Industrial Property Number
      2005-242956
    • Filing Date
      2005-08-24
    • Data Source
      KAKENHI-PROJECT-16092210
  • [Presentation] Design methods of an RSFQ circuit composed of clocked gates and clockless gates2022

    • Author(s)
      Takagi Naofumi
    • Organizer
      2022 JSPS 146th Committee International Symposium on Superconductor Electronics, 15th SSV, 4th QCCC
    • Invited / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18H05211
  • [Presentation] Logic Functions Realized Using Clockless Gates for Rapid Single-Flux-Quantum Circuits2021

    • Author(s)
      Takahiro Kawaguchi, Kazuyoshi Takagi, and Naofumi Takagi
    • Organizer
      The 23rd Workshop on Synthesis And System Integration of Mixed Information Technologies
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18H05211
  • [Presentation] SFQ回路を用いた超伝導コンピュータの開発2021

    • Author(s)
      高木直史
    • Organizer
      2021年電子情報通信学会総合大会
    • Invited
    • Data Source
      KAKENHI-PROJECT-18H05211
  • [Presentation] A Comparison of Clocking Schemes for SFQ Circuits2020

    • Author(s)
      Takahiro Kawaguchi, Kazuyoshi Takagi, and Naofumi Takagi
    • Organizer
      13th Superconducting SFQ VLSI Workshop
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18H05211
  • [Presentation] IEEE754 binary64における指数関数の丸め困難ケースについて2020

    • Author(s)
      高木直史、高木一義
    • Organizer
      2020年電子情報通信学会総合大会
    • Data Source
      KAKENHI-PROJECT-16H02795
  • [Presentation] 逆正弦の高基数CORDICアルゴリズムのFPGA上での実現2020

    • Author(s)
      松岡裕志、高木直史、高木一義
    • Organizer
      電子情報通信学会VLSI設計技術研究会(2020-01)
    • Data Source
      KAKENHI-PROJECT-16H02795
  • [Presentation] Efficient Timing Fault Simulation of Rapid Single-Flux-Quantum Logic Circuits Considering the Pipelined Behavior2020

    • Author(s)
      Shogo Nakamura, Kazuyoshi Takagi, Nobutaka Kito, and Naofumi Takagi
    • Organizer
      The 33rd International Symposium on Superconductivity
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18H05211
  • [Presentation] A Routing Method with Wire Length Matching for RSFQ Logic Circuits Using Thin PTLs2020

    • Author(s)
      Kei Kitamura, Kazuyoshi Takagi, and Naofumi Takagi
    • Organizer
      13th Superconducting SFQ VLSI Workshop
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18H05211
  • [Presentation] Static Timing Analysis of an RSFQ Circuit Considering Timing Jitter2020

    • Author(s)
      Takahiro Kawaguchi, Kazuyoshi Takagi, and Naofumi Takagi
    • Organizer
      The 33rd International Symposium on Superconductivity
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18H05211
  • [Presentation] High-density routing with wire length matching for single-flux-quantum circuits using thin passive transmission lines2020

    • Author(s)
      Kei Kitamura Masamitsu Tanaka, Takahiro Kawaguchi, Ikki Nagaoka, Kazuyoshi Takagi, Akira Fujimaki, and Naofumi Takagi
    • Organizer
      2020 Applied Superconductivity Conference (ASC 2020)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18H05211
  • [Presentation] Scan Design with Clockless Logic Gates for SFQ Circuits2019

    • Author(s)
      Takahiro Kawaguchi, Kazuyoshi Takagi, and Naofumi Takagi
    • Organizer
      32nd International Symposium on Superconductivity
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18H05211
  • [Presentation] Test Pattern Generation for Timing Faults in Rapid Single-Flux-Quantum Circuits2019

    • Author(s)
      Kazuyoshi Takagi, Mikihiro Ono, Nobutaka Kito, and Naofumi Takagi
    • Organizer
      The 22nd Workshop on Synthesis And System Integration of Mixed Information technologies
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18H05211
  • [Presentation] A Global Routing Method with Wire Length Budgeting for PTL Routing of SFQ Logic Circuits2019

    • Author(s)
      Kei Kitamura, Kazuyoshi Takagi, and Naofumi Takagi
    • Organizer
      32nd International Symposium on Superconductivity
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18H05211
  • [Presentation] 逆正弦・逆余弦計算の高基数CORDICアルゴリズム2019

    • Author(s)
      松岡裕志、高木直史
    • Organizer
      電子情報通信学会VLSI設計技術研究会(2019-11)
    • Data Source
      KAKENHI-PROJECT-16H02795
  • [Presentation] 超伝導高速単一磁束量子(RSFQ)回路のタイミング調節ための配線長予約を用いた概略配線手法2019

    • Author(s)
      北村圭, 高木直史, 高木一義
    • Organizer
      情報処理学会DAシンポジウム2019
    • Data Source
      KAKENHI-PROJECT-18H05211
  • [Presentation] A Global Routing Method with Wire Length Budgeting for SFQ Logic Circuits2019

    • Author(s)
      K. Kitamura, K.Takagi, N. Takagi
    • Organizer
      12th Superconducting SFQ VLSI Workshop (SSV 2019)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18H05211
  • [Presentation] Encoder/Decoder for the Compound Signal of Data and Clock2019

    • Author(s)
      T. Kawaguchi, K.Takagi, N. Takagi
    • Organizer
      12th Superconducting SFQ VLSI Workshop (SSV 2019)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18H05211
  • [Presentation] Placement and Routing Methods Based on Mixed Wiring of JTLs and PTLs for RSFQ Circuits2019

    • Author(s)
      Takashi Dejima, *Kazuyoshi Takagi, and Naofumi Takagi
    • Organizer
      17th International Superconductive Electronics Conference
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18H05211
  • [Presentation] A Hierarchical Placement Method with Cell Clustering for Rapid-Single-Flux-Quantum Circuits2019

    • Author(s)
      T. Dejima, K.Takagi, N. Takagi
    • Organizer
      12th Superconducting SFQ VLSI Workshop (SSV 2019)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18H05211
  • [Presentation] 大規模SFQ論理回路のパルス到着タイミングを最適化する配置手法2018

    • Author(s)
      北村圭、高木一義、高木直史
    • Organizer
      電子情報通信学会エレクトロニクスソサイエティ大会
    • Data Source
      KAKENHI-PROJECT-18H05211
  • [Presentation] 超伝導単一磁束量子(SFQ)回路設計のためのタイミング制約を考慮した自動配置アルゴリズム2018

    • Author(s)
      出島貴史、高木一義、高木直史
    • Organizer
      情報処理学会 DAシンポジウム2018
    • Data Source
      KAKENHI-PROJECT-18H05211
  • [Presentation] 倍精度浮動小数点正弦・余弦関数のFPGA向き計算法2018

    • Author(s)
      豊島悠紀夫、高木直史
    • Organizer
      電子情報通信学会  コンピュータシステム研究会
    • Data Source
      KAKENHI-PROJECT-16H02795
  • [Presentation] 倍精度浮動小数点対数関数のFPGA向き計算法2017

    • Author(s)
      藤原康史、高木一義、高木直史
    • Organizer
      電子情報通信学会コンピュータシステム研究会
    • Place of Presentation
      具志川農村環境改善センター(沖縄県島尻郡久米島町)
    • Year and Date
      2017-03-09
    • Data Source
      KAKENHI-PROJECT-16H02795
  • [Presentation] 高基数STL法を用いたFPGA向き指数関数計算法2017

    • Author(s)
      藤原康史、高木一義、高木直史
    • Organizer
      電子情報通信学会  リコンフィギャラブルシステム研究会
    • Data Source
      KAKENHI-PROJECT-16H02795
  • [Presentation] 高基数STL法を用いたFPGA向き対数関数計算法2017

    • Author(s)
      藤原康史、高木一義、高木直史
    • Organizer
      情報処理学会 DAシンポジウム
    • Data Source
      KAKENHI-PROJECT-16H02795
  • [Presentation] プログラマブルSoCのためのシステム設計環境におけるフロントエンドの実装と事例評価2014

    • Author(s)
      東遼平、高瀬英希、高木一義、高木直史
    • Organizer
      ETNET2014
    • Place of Presentation
      沖縄県石垣市  ICT文化ホール
    • Data Source
      KAKENHI-PROJECT-24300019
  • [Presentation] 部分二重化を用いた微小誤りを許容するオンライン誤り検出可能な浮動小数点乗算器2014

    • Author(s)
      鬼頭信貴、秋元一志、高木直史
    • Organizer
      電子情報通信学会ディペンダブルコンピューティング研究会
    • Place of Presentation
      東京都港区 機械振興会館
    • Year and Date
      2014-06-20
    • Data Source
      KAKENHI-PROJECT-24300019
  • [Presentation] プログラマブルSoCのためのシステム設計環境の検討とSW-HWインタフェース生成手法の実装2014

    • Author(s)
      東遼平、高瀬英希、高木一義、高木直史
    • Organizer
      情報処理学会システムLSI設計技術研究会
    • Place of Presentation
      横浜市 慶応義塾大学日吉キャンパス
    • Data Source
      KAKENHI-PROJECT-24300019
  • [Presentation] 行列多項式 I+A+A^2+…+A^{N-1} の計算における乗算回数について2014

    • Author(s)
      松本耕太郎、高木直史、高木一義
    • Organizer
      電子情報通信学会コンピュテーション研究会
    • Place of Presentation
      豊橋市 豊橋技術科学大学
    • Year and Date
      2014-09-02
    • Data Source
      KAKENHI-PROJECT-24300019
  • [Presentation] 組込みマルチコアシステムにおけるタスク割付およびスクラッチパッドメモリ割当の同時最適化2013

    • Author(s)
      松本耕太朗、高瀬英希、高木一義、高木直史
    • Organizer
      情報処理学会 DAシンポジウム
    • Place of Presentation
      岐阜県下呂市 ホテル水明館
    • Data Source
      KAKENHI-PROJECT-24300019
  • [Presentation] 組込みシステム向けDVFSアルゴリズムのリアルタイムOSへの実装および比較評価2013

    • Author(s)
      岩田淳、高瀬英希、高木一義、高木直史
    • Organizer
      第12回情報科学技術フォーラム
    • Place of Presentation
      鳥取市 鳥取大学
    • Data Source
      KAKENHI-PROJECT-24300019
  • [Presentation] IEEE754標準丸めに対応した斜辺計算のためのVLSIアルゴリズム2013

    • Author(s)
      矢高裕之、高木直史
    • Organizer
      デザインガイア2013
    • Place of Presentation
      鹿児島市 鹿児島県文化センター
    • Data Source
      KAKENHI-PROJECT-24300019
  • [Presentation] 高位合成における非一様依存性を持つ入れ子ループ向けのバッファ構成法2013

    • Author(s)
      須田瑛太、高瀬英希、高木一義、高木直史
    • Organizer
      デザインガイア2013
    • Place of Presentation
      鹿児島市 鹿児島県文化センター
    • Data Source
      KAKENHI-PROJECT-24300019
  • [Presentation] 桁上げビットの二重化によるセルフチェッキング桁上げ先見加算器2013

    • Author(s)
      三苫晃弘、鬼頭信貴、高木直史
    • Organizer
      電子情報通信学会ディペンダブルコンピューティング研究会
    • Place of Presentation
      対馬市交流センター(長崎県対馬市)
    • Year and Date
      2013-03-14
    • Data Source
      KAKENHI-PROJECT-24300019
  • [Presentation] 浮動小数点演算器アレイの構成のための評価環境2013

    • Author(s)
      伊藤勇也、高木一義、高木直史, 他
    • Organizer
      電子情報通信学会コンピュータシステム研究会
    • Place of Presentation
      対馬市交流センター(長崎県対馬市)
    • Year and Date
      2013-03-14
    • Data Source
      KAKENHI-PROJECT-24300019
  • [Presentation] 剰余符号を用いたオンライン誤り検出可能な浮動小数点乗算器2013

    • Author(s)
      山口大樹、鬼頭信貴、高木直史
    • Organizer
      第69回FTC研究会
    • Place of Presentation
      山口市 かんぽの宿湯田
    • Data Source
      KAKENHI-PROJECT-24300019
  • [Presentation] 部分二重化を用いたオンライン誤り検出可能な乗算器2013

    • Author(s)
      秋元一志、鬼頭信貴、高木直史
    • Organizer
      電子情報通信学会ディペンダブルコンピューティング研究会
    • Place of Presentation
      対馬市交流センター(長崎県対馬市)
    • Year and Date
      2013-03-14
    • Data Source
      KAKENHI-PROJECT-24300019
  • [Presentation] High-Level Synthesis for Nested Loop Kernels with Non-Uniform Dependencies2013

    • Author(s)
      Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
    • Organizer
      SASIMI2013
    • Place of Presentation
      札幌市 ホテル札幌ガーデンパレス
    • Data Source
      KAKENHI-PROJECT-24300019
  • [Presentation] 剰余検査によるオンライン誤り検出可能な浮動小数点乗算器2013

    • Author(s)
      山口大樹、鬼頭信貴、高木直史
    • Organizer
      情報処理学会 DAシンポジウム
    • Place of Presentation
      岐阜県下呂市 ホテル水明館
    • Data Source
      KAKENHI-PROJECT-24300019
  • [Presentation] 桁上げ生成二重化によるフォールドセキュアな並列プレフィクス加算器の構成法2012

    • Author(s)
      鬼頭信貴、高木直史
    • Organizer
      電子情報通信学会ディペンダブルコンピューティング研究会
    • Place of Presentation
      九州大学医学部百周年講堂(福岡市)
    • Year and Date
      2012-11-28
    • Data Source
      KAKENHI-PROJECT-24300019
  • [Presentation] Timing Optimization Methods for Superconducting SFQ Circuits2010

    • Author(s)
      Kazuyoshi Takagi, Shota Takeshima, Motoki Sato, Masamitsu Tanaka, Naofumi Takagi
    • Organizer
      Superconducting SFQ VLSI Workshop (SSV 2010)
    • Place of Presentation
      Yokohama National University.
    • Year and Date
      2010-01-12
    • Data Source
      KAKENHI-PROJECT-18080008
  • [Presentation] Timing Optimization Methods for Superconducting SFQ Circuits2010

    • Author(s)
      Kazuyoshi Takagi, Shota Takeshima, Motoki Sato, Masamitsu Tanaka, Naofumi Takagi
    • Organizer
      Superconducting SFQ VLSI Workshop (SSV 2010)
    • Place of Presentation
      横浜市
    • Year and Date
      2010-01-12
    • Data Source
      KAKENHI-PROJECT-18080008
  • [Presentation] A Verification Method for Pipeline Processing Behavior of Single-Flux-Quantum Circuits by Equivalence Checking of Timed Logic Formulae2010

    • Author(s)
      Motoki Sato, Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi
    • Organizer
      Superconducting SFQ VLSI Workshop (SSV 2010)
    • Place of Presentation
      Yokohama National University
    • Year and Date
      2010-01-12
    • Data Source
      KAKENHI-PROJECT-18080008
  • [Presentation] A Verification Method for Pipeline Processing Behavior of Single-Flux-Quantum Circuits by Equivalence Checking of Timed Logic Formulae2010

    • Author(s)
      Motoki Sato, Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi
    • Organizer
      Superconducting SFQ VLSI Workshop (SSV 2010)
    • Place of Presentation
      横浜市
    • Year and Date
      2010-01-12
    • Data Source
      KAKENHI-PROJECT-18080008
  • [Presentation] Verification Method of Pipeline Processing Behavior of SFQ Circuits2009

    • Author(s)
      Motoki Sato, Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi
    • Organizer
      Superconducting SFQ VLSI Workshop (SSV 2009)
    • Place of Presentation
      福岡市
    • Year and Date
      2009-06-15
    • Data Source
      KAKENHI-PROJECT-18080008
  • [Presentation] SFQ回路のためのレイアウトを考慮したスキューのあるクロック木の構成法2009

    • Author(s)
      伊藤祐喜、高木一義、高木直史
    • Organizer
      電子情報通信学会総合大会
    • Place of Presentation
      愛媛大学
    • Year and Date
      2009-03-20
    • Data Source
      KAKENHI-PROJECT-18080008
  • [Presentation] 単一磁束量子回路のためのパイプライン検証手法2009

    • Author(s)
      佐藤元紀、田中雅光、高木一義、高木直史
    • Organizer
      2009年電子情報通信学会エレクトロニクスソサイエティ大会
    • Place of Presentation
      新潟市
    • Year and Date
      2009-09-18
    • Data Source
      KAKENHI-PROJECT-18080008
  • [Presentation] パイプライン動作を考慮した単一磁束量子回路のための論理設計検証手法2009

    • Author(s)
      佐藤元紀、田中雅光、高木一義、高木直史
    • Organizer
      電子情報通信学会SCE研究会
    • Place of Presentation
      東京都
    • Year and Date
      2009-10-20
    • Data Source
      KAKENHI-PROJECT-18080008
  • [Presentation] A Method for Layout-Driven Skewed Clock Tree Synthesis for SFQ Circuits2009

    • Author(s)
      Kazuyoshi Takagi, Yuki Ito, Masamitsu Tanaka, Naofumi Takagi
    • Organizer
      Superconducting SFQ VLSI Workshop (SSV 2009)
    • Place of Presentation
      福岡市
    • Year and Date
      2009-06-15
    • Data Source
      KAKENHI-PROJECT-18080008
  • [Presentation] 多層配線単三磁束量子回路のための自動配線手法2008

    • Author(s)
      竹島将太、田中雅光、高木三義、高木直史
    • Organizer
      電子情報通信学会超伝導エレクトロニクス研究会
    • Place of Presentation
      産業技術総合研究所
    • Year and Date
      2008-10-30
    • Data Source
      KAKENHI-PROJECT-18080008
  • [Presentation] Level-testability of multi-operand adders2008

    • Author(s)
      Nobutaka Kito, Naofumi Takagi
    • Organizer
      17th Asia Test Symposium
    • Place of Presentation
      京王プラザホテル札幌(札幌市)
    • Year and Date
      2008-11-26
    • Data Source
      KAKENHI-PROJECT-20300016
  • [Presentation] Test generation for multi-operand adders consisting of full adders2008

    • Author(s)
      鬼頭信貴, 高木直史
    • Organizer
      電子情報通信学会ディペンダブルコンピューティング研究会
    • Place of Presentation
      機械振興会館(東京都港区)
    • Year and Date
      2008-06-20
    • Data Source
      KAKENHI-PROJECT-20300016
  • [Presentation] Computer-Aided Design of Superconducting SFQ Digital Circuits2008

    • Author(s)
      Kazuyoshi Takagi, Naofumi Takagi, Masamitsu Tanaka, Koji Obata, Yuki Ito
    • Organizer
      Superconducting SFQ VLSI Workshop (SSV 2008)
    • Place of Presentation
      Yokohama National University
    • Year and Date
      2008-03-17
    • Data Source
      KAKENHI-PROJECT-18080008
  • [Presentation] 多層配線単一磁束量子回路のための自動配線手法2008

    • Author(s)
      竹島将太、田中雅光、高木一義、高木直史
    • Organizer
      電子情報通信学会超伝導エレクトロニクス研究会
    • Place of Presentation
      産業技術総合研究所
    • Year and Date
      2008-10-30
    • Data Source
      KAKENHI-PROJECT-18080008
  • [Presentation] 単一磁束量子回路による冗長2進表現を用いたシストリック開平器の設計2007

    • Author(s)
      田中雅光、小畑幸嗣、高木一義、高木直史
    • Organizer
      電子情報通信学会エレクトロニクスソサイエティ大会
    • Place of Presentation
      鳥取大学
    • Year and Date
      2007-09-11
    • Data Source
      KAKENHI-PROJECT-18080008
  • [Presentation] 配線遅延を考慮したハードウェアアルゴリズムの評価2007

    • Author(s)
      長瀬哲也, 高木一義, 高木直史
    • Organizer
      電子情報通信学会コンピュテーション研究会
    • Place of Presentation
      広島大学(東広島市)
    • Year and Date
      2007-12-14
    • Data Source
      KAKENHI-PROJECT-16092210
  • [Presentation] シストリックアーキテクチャに基づく高スループットsfqビットシリアル浮動小数点乗算器2007

    • Author(s)
      小畑幸嗣、古田卓也、高木一義、高木直史
    • Organizer
      電子情報通信学会エレクトロニクスソサイエティ大会
    • Place of Presentation
      鳥取市
    • Year and Date
      2007-09-11
    • Data Source
      KAKENHI-PROJECT-18080008
  • [Presentation] シストリックアーキテクチャに基づく高スループットSFQビットシリアル浮動小数点乗算器2007

    • Author(s)
      小畑幸嗣、古田卓也、高木一義、高木直史
    • Organizer
      電子情報通信学会エレクトロニクスソサイエティ大会
    • Place of Presentation
      鳥取市
    • Year and Date
      2007-09-11
    • Data Source
      KAKENHI-PROJECT-18080008
  • [Presentation] 2つの浮動小数点積和演算器を用いた複素数乗算器

    • Author(s)
      高田雄平、高木直史、高木一義
    • Organizer
      デザインガイア2014(電子情報通信学会コンピュータシステム研究会)
    • Place of Presentation
      別府市 ビーコンプラザ(別府国際コンベンションセンター)
    • Year and Date
      2014-11-26 – 2014-11-28
    • Data Source
      KAKENHI-PROJECT-24300019
  • [Presentation] 部分二重化を用いたオンライン誤り検出可能な浮動小数点乗算器の設計と評価

    • Author(s)
      鬼頭信貴、秋元一志、高木直史
    • Organizer
      ETNET2015(電子情報通信学会ディペンダブルコンピューティング研究会)
    • Place of Presentation
      奄美市 奄美社会福祉協議会
    • Year and Date
      2015-03-06 – 2015-03-07
    • Data Source
      KAKENHI-PROJECT-24300019
  • [Presentation] 2つの浮動小数点倍精度加算器を用いた仮数部104ビット拡張倍精度加算器

    • Author(s)
      矢高裕之、高木直史、高木一義
    • Organizer
      デザインガイア2014(電子情報通信学会コンピュータシステム研究会)
    • Place of Presentation
      別府市 ビーコンプラザ(別府国際コンベンションセンター)
    • Year and Date
      2014-11-26 – 2014-11-28
    • Data Source
      KAKENHI-PROJECT-24300019
  • 1.  OGINO Hiroyuki (40144323)
    # of Collaborated Projects: 9 results
    # of Collaborated Products: 0 results
  • 2.  YAJIMA Shuzo (20025901)
    # of Collaborated Projects: 8 results
    # of Collaborated Products: 0 results
  • 3.  HIRAISHI Hiromi (40093299)
    # of Collaborated Projects: 8 results
    # of Collaborated Products: 0 results
  • 4.  KAZUYOSHI Takagi (70273844)
    # of Collaborated Projects: 7 results
    # of Collaborated Products: 85 results
  • 5.  ISHIURA Nagisa (60193265)
    # of Collaborated Projects: 5 results
    # of Collaborated Products: 0 results
  • 6.  TAKENAGA Yasuhiko (20236491)
    # of Collaborated Projects: 4 results
    # of Collaborated Products: 0 results
  • 7.  HAMAGUCHI Kiyoharu (80238055)
    # of Collaborated Projects: 3 results
    # of Collaborated Products: 0 results
  • 8.  IWAMA Kazuo (50131272)
    # of Collaborated Projects: 3 results
    # of Collaborated Products: 0 results
  • 9.  NAKAMURA Kazuhiro (90335076)
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 0 results
  • 10.  KAWAKUBO Kazuo (10186067)
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 0 results
  • 11.  YASUURA Hiroto (80135540)
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 0 results
  • 12.  YASUOKA Kouichi (20230211)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 13.  Fujimaki Akira (20183931)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 1 results
  • 14.  牧瀬 圭正 (60363321)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 15.  山下 太郎 (60567254)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 16.  吉川 信行 (70202398)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 17.  NISHINAGA Nozomu
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 18.  鬼頭 信貴
    # of Collaborated Projects: 0 results
    # of Collaborated Products: 4 results

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