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Natsui Masanori  夏井 雅典

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NATSUI Masanori  夏井 雅典

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Researcher Number 10402661
Other IDs
Affiliation (Current) 2025: 東北大学, 電気通信研究所, 准教授
Affiliation (based on the past Project Information) *help 2016 – 2025: 東北大学, 電気通信研究所, 准教授
2008 – 2013: 東北大学, 電気通信研究所, 助教
2006 – 2008: 豊橋技術科学大学, 工学部, 助教
2007: 豊橋技術科学大学, 工学部, 助授
Review Section/Research Field
Principal Investigator
Basic Section 60040:Computer system-related / Intensification of Artifact Systems / Computer system/Network / Sections That Are Subject to Joint Review: Basic Section60040:Computer system-related , Basic Section60090:High performance computing-related / Basic Section 60090:High performance computing-related
Except Principal Investigator
Medium-sized Section 60:Information science, computer engineering, and related fields / Computer system / Electron device/Electronic equipment / Media informatics/Database / Computer system/Network
Keywords
Principal Investigator
集積回路 / 高信頼化 / IoT / 計算機システム / スピントロニクス / 不揮発ロジック / 知的環境適応型LSI設計技術 / 脳型LSI / 不揮発素子 / ディペンダブル・コンピューティング … More / 最適化アルゴリズム / 誤り訂正技術 / ディペンダブルコンピューティング / LSI設計技術 / 半導体超微細化 / 多値集積回路 / 先端機能デバイス / 回路設計技術 / VLSI設計技術 / ソフトコンピューティング / アナログ回路合成 / 多変量解析 / 遺伝的アルゴリズム / 回路合成 / 進化的計算 … More
Except Principal Investigator
脳型ハードウェア / 不揮発性ロジック / 非同期式回路 / ばらつき補正機能 / はらつき補正機能 / MTJデバイス / ロジックLSI / 高速・低電力回路技術 / ダイ・ハード回路 / IoT応用 / 計算機システム / ダーク・シリコンLSI / CMOS/MTJハイブリッド回路 / 不揮発ロジック / 脳型情報処理 / 最適化技術 / 新機能デバイス / バラつき補正技術 / 集積回路 / 回路設計技術 / 非調和成分 / 共振型くし形フィルタ / ノッチ型くし形フィルタ / 音源分離 / 低音域 / 音高推定困難和音 / くし形フィルタ / 連結処理 / 打楽器音 / 広音域 / 多和音 / 音高推定 / 非同期式制御 / 複号化 / 符号化 / 高速伝送技術 / LDPC符号 / 2線符号 / 非同期通信 / 多値VLSI技術 / 誤り訂正符号 / 情報システム / 高速伝送回路 / 情報通信工学 / 情報機器 Less
  • Research Projects

    (11 results)
  • Research Products

    (196 results)
  • Co-Researchers

    (13 People)
  •  高安定・高エネルギー効率な間欠演算処理を実現する不揮発ロジックLSIシステム基盤Principal Investigator

    • Principal Investigator
      夏井 雅典
    • Project Period (FY)
      2025 – 2028
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Review Section
      Basic Section 60040:Computer system-related
      Basic Section 60090:High performance computing-related
      Sections That Are Subject to Joint Review: Basic Section60040:Computer system-related , Basic Section60090:High performance computing-related
    • Research Institution
      Tohoku University
  •  Development of a high-speed and ultra-low-power die-hard logic LSI fundamental technology for IoT applications

    • Principal Investigator
      羽生 貴弘
    • Project Period (FY)
      2021 – 2024
    • Research Category
      Grant-in-Aid for Scientific Research (A)
    • Review Section
      Medium-sized Section 60:Information science, computer engineering, and related fields
    • Research Institution
      Tohoku University
  •  スピントロニクスベース高性能・省電力・高信頼IoTセンサノードの基盤研究開発Principal Investigator

    • Principal Investigator
      夏井 雅典
    • Project Period (FY)
      2021 – 2024
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Review Section
      Basic Section 60040:Computer system-related
    • Research Institution
      Tohoku University
  •  VLSI platform with intelligent environment adaptation technology and its application to highly reliable brain LSI systemsPrincipal Investigator

    • Principal Investigator
      NATSUI MASANORI
    • Project Period (FY)
      2017 – 2022
    • Research Category
      Fund for the Promotion of Joint International Research (Fostering Joint International Research)
    • Research Field
      Intensification of Artifact Systems
    • Research Institution
      Tohoku University
  •  Development of fully autonomous error-correctable VLSI design technology and its application to brain-inspired LSI systemPrincipal Investigator

    • Principal Investigator
      NATSUI Masanori
    • Project Period (FY)
      2016 – 2018
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      Intensification of Artifact Systems
    • Research Institution
      Tohoku University
  •  Fundamental Technology Development of Dark-Silicon Logic LSI for Brain-Inspired Computing

    • Principal Investigator
      Hanyu Takahiro
    • Project Period (FY)
      2016 – 2020
    • Research Category
      Grant-in-Aid for Scientific Research (S)
    • Research Field
      Computer system
    • Research Institution
      Tohoku University
  •  Nonvolatile-device-based PVT-variation-resilient VLSI system

    • Principal Investigator
      HANYU TAKAHIRO
    • Project Period (FY)
      2010 – 2013
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      Electron device/Electronic equipment
    • Research Institution
      Tohoku University
  •  Systematic Design Scheme for Process-Variation-Free Highly Dependable Multiple-Valued VLSIPrincipal Investigator

    • Principal Investigator
      NATSUI Masanori
    • Project Period (FY)
      2009 – 2011
    • Research Category
      Grant-in-Aid for Young Scientists (B)
    • Research Field
      Computer system/Network
    • Research Institution
      Tohoku University
  •  STUDY OF MUSICAL SIGNAL ANALYSIS AND ITS APPLICATIONS TO INFORMATION THECHNOLOGY

    • Principal Investigator
      TADOKORO Yoshiaki
    • Project Period (FY)
      2007 – 2008
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      Media informatics/Database
    • Research Institution
      Toyohashi University of Technology
  •  Implementation of a High-Speed LDPC Decoder LSI Based on a Multiple-Valued Full-Duplex Data-Transfer Technique

    • Principal Investigator
      HANYU Takahiro
    • Project Period (FY)
      2006 – 2008
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      Computer system/Network
    • Research Institution
      Tohoku University
  •  アナログLSIの進化的合成システムの開発に関する研究Principal Investigator

    • Principal Investigator
      夏井 雅典
    • Project Period (FY)
      2006 – 2007
    • Research Category
      Grant-in-Aid for Young Scientists (B)
    • Research Field
      Computer system/Network
    • Research Institution
      Toyohashi University of Technology

All 2023 2022 2021 2020 2019 2018 2017 2016 2013 2012 2011 2010 2009 2008 2007

All Journal Article Presentation Book

  • [Book] Beyond MRAM: Nonvolatile Logic-in-Memory VLSI, Chapter 7 in Book: Introduction to Magnetic Random-Access Memory2016

    • Author(s)
      Takahiro Hanyu, Tetsuo Endoh, Shoji Ikeda, Tadahiko Sugibayashi, Naoki Kasai, Daisuke Suzuki, Masanori Natsui, Hiroki Koike, and Hideo Ohno
    • Total Pages
      264
    • Publisher
      Wiley-IEEE Press
    • ISBN
      9781119009740
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Journal Article] Design of a Nonvolatile-Register-Embedded RISC-V CPU with Software-Controlled Data-Retention and Hardware-Acceleration Functions2023

    • Author(s)
      M. Natsui, K. Sakamoto, and T. Hanyu
    • Journal Title

      Memories - Materials, Devices, Circuits and Systems

      Volume: 4 Pages: 100035-100035

    • DOI

      10.1016/j.memori.2023.100035

    • Peer Reviewed / Open Access
    • Data Source
      KAKENHI-PROJECT-17KK0001, KAKENHI-PROJECT-23K21651, KAKENHI-PROJECT-21H04868
  • [Journal Article] Dynamic activation of power-gating-switch configuration for highly reliable nonvolatile large-scale integrated circuits2022

    • Author(s)
      F. Zhong, M. Natsui, and T. Hanyu
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: 61

    • DOI

      10.35848/1347-4065/ac461a

    • Peer Reviewed / Open Access
    • Data Source
      KAKENHI-PROJECT-17KK0001, KAKENHI-PROJECT-23K21651
  • [Journal Article] Design of a highly reliable nonvolatile flip-flop incorporating a common-mode write error detection capability2021

    • Author(s)
      M. Natsui, G. Yamagishi, and T. Hanyu
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: 60 Issue: SB Pages: SBBB02-SBBB02

    • DOI

      10.35848/1347-4065/abdcb0

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-17KK0001, KAKENHI-PROJECT-23K21651
  • [Journal Article] New-Paradigm Logic-LSI Design Technology Based on Nonvolatile Storage Functionality and Its Future Prospects2021

    • Author(s)
      夏井 雅典、羽生 貴弘
    • Volume
      J104-C
    • Issue
      6
    • Pages
      185-192
    • DOI

      10.14923/transelej.2020JCI0011

    • ISSN
      1881-0217
    • Year and Date
      2021-06-01
    • Language
      Japanese
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-16H06300, KAKENHI-PROJECT-21H04868
  • [Journal Article] 不揮発記憶機能が拓く新概念ロジックLSI設計技術とその将来展望2021

    • Author(s)
      夏井雅典, 羽生貴弘
    • Journal Title

      電子情報通信学会論文誌C

      Volume: J104-C Pages: 185-192

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Journal Article] 不揮発記憶機能が拓く新概念ロジックLSI設計技術とその将来展望2021

    • Author(s)
      夏井雅典, 羽生貴弘
    • Journal Title

      電子情報通信学会論文誌C

      Volume: Vol.J104-C, No.6 Pages: 185-192

    • Peer Reviewed / Open Access
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Journal Article] Impact of MTJ-Based Nonvolatile Circuit Techniques for Energy-Efficient Binary Neural Network Hardware2020

    • Author(s)
      M. Natsui, T. Chiba and T. Hanyu
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: 59 Issue: 5 Pages: 050602-050602

    • DOI

      10.35848/1347-4065/ab82ae

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Journal Article] Design of an energy-efficient XNOR gate based on MTJ-based nonvolatile logic-in-memory architecture for binary neural network hardware2019

    • Author(s)
      Natsui Masanori、Chiba Tomoki、Hanyu Takahiro
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: 58 Issue: SB Pages: SBBB01-SBBB01

    • DOI

      10.7567/1347-4065/aafb4d

    • NAID

      210000135331

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-17KK0001, KAKENHI-PROJECT-16KT0187
  • [Journal Article] A 47.14μW 200MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications2019

    • Author(s)
      M. Natsui, D. Suzuki, A. Tamakoshi, T. Watanabe, H. Honjo, H. Koike, T. Nasuno, Y. Ma, T. Tanigawa, Y. Noguchi, M. Yasuhira, H. Sato, S. Ikeda, H. Ohno, T. Endoh, and T. Hanyu
    • Journal Title

      IEEE Journal of Solid State Circuits

      Volume: 54 Issue: 11 Pages: 2991-3004

    • DOI

      10.1109/jssc.2019.2930910

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Journal Article] Design of a memory-access controller with 3.71-times-enhanced energy efficiency for Internet-of-Things-oriented nonvolatile microcontroller unit2018

    • Author(s)
      M. Natsui and T. Hanyu
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: 57/4S Issue: 4S Pages: 04FN03-04FN03

    • DOI

      10.7567/jjap.57.04fn03

    • NAID

      210000148986

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Journal Article] Design of MTJ-Based nonvolatile logic gates for quantized neural networks2018

    • Author(s)
      Natsui Masanori、Chiba Tomoki、Hanyu Takahiro
    • Journal Title

      Microelectronics Journal

      Volume: 82 Pages: 13-21

    • DOI

      10.1016/j.mejo.2018.10.005

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-17KK0001, KAKENHI-PROJECT-16KT0187
  • [Journal Article] Design of a Variation-Resilient Single-Ended Nonvolatile 6-Input Lookup Table Circuit with a Redundant-MTJ-Based Active Load for Smart IoT Applications2017

    • Author(s)
      D. Suzuki, M. Natsui, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu
    • Journal Title

      Institute of Engineering Technology (IET), Electronics Letters

      Volume: 53, 7 Pages: 456-458

    • Peer Reviewed / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Journal Article] Design of a Variation-Resilient Single-Ended Nonvolatile 6-Input Lookup Table Circuit with a Redundant-MTJ-Based Active Load for Smart IoT Applications2017

    • Author(s)
      D. Suzuki, M. Natsui, A. Mochizuki, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu
    • Journal Title

      IET Electronics Letters

      Volume: 53 Issue: 7 Pages: 456-458

    • DOI

      10.1049/el.2016.4233

    • Peer Reviewed / Open Access
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Journal Article] Fabrication of an MTJ-Based Nonvolatile Logic-in-Memory LSI with Content-Aware Write Error Masking Scheme Achieving 92% Storage Capacity and 79% Power Reduction2017

    • Author(s)
      Masanori Natsui, Akira Tamakoshi, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: 56, 4S

    • Peer Reviewed / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Journal Article] Fabrication of an MTJ-Based Nonvolatile Logic-in-Memory LSI with Content-Aware Write Error Masking Scheme Achieving 92% Storage Capacity and 79% Power Reduction2017

    • Author(s)
      M. Natsui, A. Tamakoshi, T. Endoh, H. Ohno, and T. Hanyu
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: 56 Issue: 4S Pages: 04CN01-04CN01

    • DOI

      10.7567/jjap.56.04cn01

    • Peer Reviewed / Acknowledgement Compliant / Open Access
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Journal Article] Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing2016

    • Author(s)
      T. Hanyu, T. Endoh, D. Suzuki, H. Koike, Y. Ma, N. Onizawa, M. Natsui, S. Ikeda, and H. Ohno
    • Journal Title

      Proc. of the IEEE

      Volume: 104 Issue: 10 Pages: 1843-1863

    • DOI

      10.1109/jproc.2016.2574939

    • Peer Reviewed / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-26700003, KAKENHI-PROJECT-16K12494, KAKENHI-PROJECT-16H06300
  • [Journal Article] Design and Evaluation of a Differential Switching Gate for Low-Voltage Applications2013

    • Author(s)
      M. Natsui
    • Journal Title

      Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic

      Volume: -

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] Design and Evaluation of a Differential Switching Gate for Low-Voltage Applications2013

    • Author(s)
      M. Natsui, K. Kashiuchi, and T. Hanyu
    • Journal Title

      43rd IEEE International Symposium on Multiple-Valued Logic (ISMVL2013)

      Pages: 147-151

    • DOI

      10.1109/ismvl.2013.23

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] MTJ/MOS-Hybrid Logic-Circuit Design Flow for Nonvolatile Logic-in-Memory LSI2013

    • Author(s)
      M. Natsui, N. Sakimura, T. Sugibayashi, and T. Hanyu
    • Journal Title

      2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

      Pages: 105-108

    • DOI

      10.1109/iscas.2013.6571793

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] Design of Process-Variation-Resilient Analog Basic Components Using Magnetic-Tunnel-Junction Devices2013

    • Author(s)
      M. Natsui
    • Journal Title

      Journal of Multiple-Valued Logic and Soft Computing

      Volume: -

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] Design of Process-Variation-Resilient Analog Basic Components Using Magnetic-Tunnel-Junction Devices2013

    • Author(s)
      M. Natsui and T. Hanyu
    • Journal Title

      Journal of Multiple-Valued Logic and Soft Computing

      Volume: Vol.21, No.5-6 Pages: 597-608

    • URL

      http://www.oldcitypublishing.com/pdf/3498

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] Process-Variation-Resilient OTA Using MTJ-Based Multi-Level Resistance Control2012

    • Author(s)
      M. Natsui, T. Nagashima, and T. Hanyu
    • Journal Title

      42nd IEEE International Symposium on Multiple-Valued Logic (ISMVL2012)

      Pages: 214-219

    • DOI

      10.1109/ismvl.2012.52

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] Process-Variation-Resilient OTA Using MTJ-Based Multi-Level Resistance Control2012

    • Author(s)
      M.Natsui, T.Nagashima, T.Hanyu
    • Journal Title

      Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic

      Volume: (掲載確定)

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] Variation-Resilient Current-Mode Logic Circuit Design Using MTJ Devices2012

    • Author(s)
      Y.Kim, M.Natsui, T.Hanyu
    • Journal Title

      Proceedings of 2012 IEEE International Symposium on Circuits & Systems

      Volume: (掲載確定)

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] Scalable Serial-Configuration Scheme for MTJ/MOS-Hybrid Variation-Resilient VLSI System2012

    • Author(s)
      M. Natsui and T. Hanyu
    • Journal Title

      10th IEEE International NEWCAS Conference

      Volume: (掲載確定)

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-21700051
  • [Journal Article] Scalable Serial-Configuration Scheme for MTJ/MOS-Hybrid Variation-Resilient VLSI System2012

    • Author(s)
      M. Natsui and T. Hanyu
    • Journal Title

      10th IEEE International NEWCAS Conference (NEWCAS2012)

      Pages: 97-100

    • DOI

      10.1109/newcas.2012.6328965

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] Scalable Serial-Configuration Scheme for MTJ/MOS-Hybrid Variation-Resilient VLSI System2012

    • Author(s)
      M. Natsui
    • Journal Title

      Proceedings of the 10th IEEE International NEWCAS Conference

      Volume: - Pages: 97-100

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] Low-Energy Pipelined Multiple-Valued Current-Mode Circuit Based on Current-Level Control Technique2012

    • Author(s)
      M. Natsui, T. Arimitsu and T. Hanyu
    • Journal Title

      Journal of Multiple-Valued Logic and Soft Computing

      Volume: Vol.19, No.1-3 Pages: 219-231

    • URL

      http://www.oldcitypublishing.com/pdf/2910

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] Variation-Resilient Current-Mode Logic Circuit Design Using MTJ Devices2012

    • Author(s)
      Y. Kim, M. Natsui and T. Hanyu
    • Journal Title

      2012 IEEE International Symposium on Circuits & Systems (ISCAS2012)

      Pages: 2705-2708

    • DOI

      10.1109/iscas.2012.6271866

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] Variation-Resilient Current-Mode Logic Circuit Design Using MTJ Devices2012

    • Author(s)
      Y. Kim, M. Natsui M and T. Hanyuand
    • Journal Title

      Proceedings of 2012 IEEE International Symposium on Circuits & Systems

      Volume: (掲載確定)

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-21700051
  • [Journal Article] Process-Variation-Resilient OTA Using MTJ-Based Multi-Level Resistance Control2012

    • Author(s)
      M. Natsui
    • Journal Title

      Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic

      Volume: - Pages: 214-219

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] Variation-Resilient Current-Mode Logic Circuit Design Using MTJ Devices2012

    • Author(s)
      Y.Kim, M.Natsui, T.Hanyu
    • Journal Title

      Proceedings of 2012 IEEE International Symposium on Circuits & Systems

      Volume: (掲載確定)

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-21700051
  • [Journal Article] Low-Energy Pipelined Multiple-Valued Current-Mode Circuit Based on Current-Level Control Technique2012

    • Author(s)
      M.Natsui, T.Arimitsu, T.Hanyu
    • Journal Title

      Journal of Multiple-Valued Logic and Soft Computing

      Volume: (未定)(掲載確定)

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] MTJ-Based Optimal Vth-Tuning Technique for a Process-Variation-Aware VLSI processor2011

    • Author(s)
      M.Natsui, Y.Kim, T.Hanyu
    • Journal Title

      Proceedings of the 56th Magnetism and Magnetic Materials Conference

      Pages: 480-481

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] MTJ-Based Optimal Vth-Tuning Technique for a Process-Variation-Aware VLSI processor2011

    • Author(s)
      M. Natsui, Y. Kim and T. Hanyu
    • Journal Title

      Proceedings of the 56th Magnetism and Magnetic Materials Conference

      Pages: 480-481

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-21700051
  • [Journal Article] MTJ-Based Optimal Vth-Tuning Technique for a Process-Variation-Aware VLSI processor2011

    • Author(s)
      M. Natsui, Y. Kim and T. Hanyu
    • Journal Title

      The 56th Magnetism and Magnetic Materials Conference (MMM2011)

      Pages: 480-481

    • URL

      http://www.magnetism.org/

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] MTJ-Based Optimal Vth-Tuning Technique for a Process-Variation-Aware VLSI processor2011

    • Author(s)
      M.Natsui, Y.Kim, T.Hanyu
    • Journal Title

      Proceedings of the 56th Magnetism and Magnetic Materials Conference

      Pages: 480-481

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-21700051
  • [Journal Article] Process-Variation-Aware VLSI Design Using Emerging Functional Devices and Its Impact2010

    • Author(s)
      M. Natsui and T. Hanyu
    • Journal Title

      Booklet of the 19th International Workshop on Post-Binary ULSI Systems

      Pages: 20-25

    • Data Source
      KAKENHI-PROJECT-21700051
  • [Journal Article] Low-Energy Pipelined Multiple-Valued Current-Mode Circuit with 8-Level Static Current-Source Control2010

    • Author(s)
      M. Natsui, T. Arimitsu and T. Hanyu
    • Pages
      235-240
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-21700051
  • [Journal Article] Synthesis of current mirrors based on evolutionary graph generation with transmigration capability2007

    • Author(s)
      M.Natsui, Y.Tadokoro, N.Homma, T.Aoki, T.Higuchi
    • Journal Title

      IEICE Electronics Express Vol. 4 No. 3

      Pages: 88-93

    • NAID

      130000088503

    • Data Source
      KAKENHI-PROJECT-18700044
  • [Presentation] Write-Energy Reduction of MTJ-Based Quantized Neural-Network Hardware2023

    • Author(s)
      K. Asano, M. Natsui, and T. Hanyu
    • Organizer
      53th IEEE International Symposium on Multiple-Valued Logic (ISMVL2023)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Presentation] 不揮発ロジックLSI技術に基づく次世代エッジコンピューティングパラダイムの展望2023

    • Author(s)
      夏井雅典
    • Organizer
      NV-FPGA Initiative 第4回公開シンポジウム
    • Invited
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Presentation] 次世代IoT社会を拓く不揮発性ロジックLSI技術とその応用展開2023

    • Author(s)
      夏井雅典
    • Organizer
      第87回半導体・集積回路技術シンポジウム
    • Invited
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Presentation] High-Performance/Low-Area Power-Gating Switch Linear Array for Energy-Efficient LSIs with an Optimum Switch-Timing Control2023

    • Author(s)
      F. Zhong, M. Natsui, and T. Hanyu
    • Organizer
      2023 IEEE International Symposium on Circuits and Systems(ISCAS2023)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Presentation] 不揮発性ロジックLSI技術に基づく次世代エッジコンピューティングの展望2023

    • Author(s)
      夏井雅典
    • Organizer
      集積回路研究会「メモリ技術と集積回路技術一般」
    • Invited
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Presentation] Design of an Error-Tolerant Nonvolatile Register for Energy-Aware Intermittent Computing2023

    • Author(s)
      K. Sakai, M. Natsui, and T. Hanyu
    • Organizer
      The 66th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2023)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Presentation] 不揮発ロジックLSI技術に基づく次世代エッジコンピューティングパラダイムの展望2023

    • Author(s)
      夏井雅典
    • Organizer
      NV-FPGA Initiative 第4回公開シンポジウム
    • Invited
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] Challenge of Energy-Efficient Edge-AI Accelerator Architecture Using Nonvolatile Logic2023

    • Author(s)
      M. Natsui, Y. Takako, A. Tamakoshi, and T. Hanyu
    • Organizer
      2023 International Symposium on Nonlinear Theory and Its Applications (NOLTA2023)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Presentation] 高位合成を用いた不揮発AIアクセラレータの高効率設計に関する基礎的研究2023

    • Author(s)
      渡邉颯音,夏井雅典,羽生貴弘
    • Organizer
      2023年度電気関係学会東北支部連合大会
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Presentation] Error-Sensitivity-Aware Write-Energy Optimization for an MTJ-Based Binarized Neural Network2023

    • Author(s)
      K. Asano, M. Natsui, and T. Hanyu
    • Organizer
      30th IEEE International Conference on Electronics Circuits and Systems (ICECS2023)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Presentation] Challenge of a Low-Power FPGA-Based CNN Accelerator Based on Nonvolatile Logic-in-Memory Circuitry2023

    • Author(s)
      D. Suzuki, M. Natsui, A. Tamakoshi, Y. Takako, and T. Hanyu
    • Organizer
      2023 International Symposium on Nonlinear Theory and Its Applications (NOLTA2023)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Presentation] Impact of Spintronics-Based Nonvolatile Hardware for AI Applications2023

    • Author(s)
      T. Hanyu, N. Onizawa, D. Suzuki, and M. Natsui
    • Organizer
      2023 International Conference on Solid State Devices and Materials (SSDM2023)
    • Invited / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Presentation] ビットエラー耐性を活用した省エネルギーニューラルネットワークの構成に関する基礎的研究2022

    • Author(s)
      浅野健,夏井雅典,羽生貴弘
    • Organizer
      2022年度電気関係学会東北支部連合大会
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Presentation] Operation-Condition-Aware Dynamic Power Gating for Nonvolatile LSIs,2022

    • Author(s)
      F. Zhong, M. Natsui, and T. Hanyu
    • Organizer
      31st International Workshop on Post-Binary ULSI Systems
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] MTJベース量子化ニューラルネットワークハードウェアの書込みエネルギー削減手法に関する研究2022

    • Author(s)
      浅野健,夏井雅典,羽生貴弘
    • Organizer
      ICD学生・若手研究会
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Presentation] Prospects of Energy-Efficient Edge-AI Accelerator Architecture Using Nonvolatile Logic2022

    • Author(s)
      M. Natsui, D. Suzuki, Y. Takako, A. Tamakoshi, and T. Hanyu
    • Organizer
      2022 International Symposium on Nonlinear Theory and Its Applications (NOLTA 2022)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-21H04868
  • [Presentation] 書込みエラー特性に基づくMTJベース不揮発レジタの制御部最適化に関する一検討2022

    • Author(s)
      酒井 楓,夏井 楓,夏井 雅典,羽生 貴弘
    • Organizer
      2022年度ICD/CAS学生・若手研究会
    • Data Source
      KAKENHI-PROJECT-21H04868
  • [Presentation] 書込みエラー検出機能を有する高信頼不揮発レジスタの構成2022

    • Author(s)
      酒井楓,夏井雅典 ,羽生貴弘
    • Organizer
      2022年度電気関係学会東北支部連合講演会
    • Data Source
      KAKENHI-PROJECT-21H04868
  • [Presentation] 不揮発ロジックLSI技術に基づく次世代エッジコンピューティングパラダイムの展望2022

    • Author(s)
      夏井雅典
    • Organizer
      NV-FPGA Initiative 第4回公開シンポジウム
    • Invited
    • Data Source
      KAKENHI-PROJECT-21H04868
  • [Presentation] Energy-Efficient Nonvolatile RISC-V CPU with a Custom Instruction-Controlled Accelerator2022

    • Author(s)
      Keisuke Sakamoto,Masanori Natsui, and Takahiro Hanyu
    • Organizer
      65th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2022)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-21H04868
  • [Presentation] 不揮発LSI向け可変パワーゲーティングスイッチ構造とその動的制御に関する研究2022

    • Author(s)
      鐘方岑,夏井雅典,羽生貴弘
    • Organizer
      ICD学生・若手研究会
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Presentation] ビットエラー耐性を活用した省エネルギーニューラルネットワークの構成に関する基礎的考察2022

    • Author(s)
      浅野健,佐々木優里,夏井雅典,羽生貴弘
    • Organizer
      2022年度電気関係学会東北支部連合講演会
    • Data Source
      KAKENHI-PROJECT-21H04868
  • [Presentation] MTJ ベース量子化ニューラルネットワークハードウェアの書込みエネルギー削減手法に関する研究2022

    • Author(s)
      浅野健, 夏井雅典, 羽生貴弘
    • Organizer
      2022年度ICD/CAS学生・若手研究会
    • Data Source
      KAKENHI-PROJECT-21H04868
  • [Presentation] Energy-Efficient Nonvolatile RISC-V CPU with a Custom Instruction-Controlled Accelerator2022

    • Author(s)
      K. Sakamoto, M. Natsui, and T. Hanyu
    • Organizer
      2022 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2022)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] MTJベース量子化ニューラルネットワークハードウェアの書込みエネルギー削減手法に関する研究2022

    • Author(s)
      浅野健,夏井雅典,羽生貴弘
    • Organizer
      ICD学生・若手研究会
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] 書込みエラー特性に基づく MTJ ベース不揮発レジスタの制御部最適化に関する一検討2022

    • Author(s)
      酒井楓,夏井雅典,羽生貴弘
    • Organizer
      ICD学生・若手研究会
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] 書込みエラー特性に基づく MTJ ベース不揮発レジスタの制御部最適化に関する一検討2022

    • Author(s)
      酒井楓,夏井雅典,羽生貴弘
    • Organizer
      ICD学生・若手研究会
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Presentation] 不揮発LSI向け可変パワーゲーティングスイッチ構造とその動的制御に関する研究2022

    • Author(s)
      鐘方岑,夏井雅典,羽生貴弘
    • Organizer
      ICD学生・若手研究会
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] Design of a Low-Power FPGA-Based CNN Accelerator Based on Nonvolatile Logic-in-Memory Circuitry2022

    • Author(s)
      D. Suzuki, M. Natsui, A. Tamakoshi, Y. Takako, and T. Hanyu
    • Organizer
      2022 International Symposium on Nonlinear Theory and Its Applications (NOLTA2022)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] ビットエラー耐性を活用した省エネルギーニューラルネットワークの構成に関する基礎的研究2022

    • Author(s)
      浅野健,夏井雅典,羽生貴弘
    • Organizer
      2022年度電気関係学会東北支部連合大会
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] 書込みエラー検出機能を有する高信頼不揮発レジスタの構成2022

    • Author(s)
      酒井楓,夏井雅典,羽生貴弘
    • Organizer
      2022年度電気関係学会東北支部連合大会
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] Prospects of Energy-Efficient Edge-AI Accelerator Architecture Using Nonvolatile Logic2022

    • Author(s)
      M. Natsui, D. Suzuki, Y. Takako, A. Tamakoshi, and T. Hanyu
    • Organizer
      2022 International Symposium on Nonlinear Theory and Its Applications (NOLTA2022)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Presentation] アクセラレータ制御命令を組み込んだRISC-Vベース省エネルギー不揮発CPUの構成2022

    • Author(s)
      坂本佳介,夏井雅典,羽生貴弘
    • Organizer
      電子情報通信学会集積回路研究会「LSIとシステムのワークショップ」
    • Data Source
      KAKENHI-PROJECT-21H04868
  • [Presentation] Prospects of Energy-Efficient Edge-AI Accelerator Architecture Using Nonvolatile Logic2022

    • Author(s)
      M. Natsui, D. Suzuki, Y. Takako, A. Tamakoshi, and T. Hanyu
    • Organizer
      2022 International Symposium on Nonlinear Theory and Its Applications (NOLTA2022)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] Operation-Condition-Aware Dynamic Power Gating for Nonvolatile LSIs2022

    • Author(s)
      Fangcen Zhong, Masanori Natsui, and Takahiro Hanyu
    • Organizer
      31st International Workshop on Post-Binary ULSI Systems
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-21H04868
  • [Presentation] 書込みエラー検出機能を有する高信頼不揮発レジスタの構成2022

    • Author(s)
      酒井楓,夏井雅典,羽生貴弘
    • Organizer
      2022年度電気関係学会東北支部連合大会
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Presentation] Operation-Condition-Aware Dynamic Power Gating for Nonvolatile LSIs2022

    • Author(s)
      F. Zhong, M. Natsui, and T. Hanyu
    • Organizer
      31st International Workshop on Post-Binary ULSI Systems
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Presentation] アクセラレータ制御命令を組み込んだRISC-Vベース省エネルギー不揮発CPUの構成2022

    • Author(s)
      坂本佳介,夏井雅典,羽生貴弘
    • Organizer
      LSIとシステムのワークショップ2022
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] Energy-Efficient Nonvolatile RISC-V CPU with a Custom Instruction-Controlled Accelerator2022

    • Author(s)
      K. Sakamoto, M. Natsui, and T. Hanyu
    • Organizer
      2022 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2022)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Presentation] アクセラレータ制御命令を組み込んだRISC-Vベース省エネルギー不揮発CPUの構成2022

    • Author(s)
      坂本佳介,夏井雅典,羽生貴弘
    • Organizer
      LSIとシステムのワークショップ2022
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Presentation] Design of a Low-Power FPGA-Based CNN Accelerator Based on Nonvolatile Logic-in-Memory Circuitry2022

    • Author(s)
      D. Suzuki, M. Natsui, A. Tamakoshi, Y. Takako, and T. Hanyu
    • Organizer
      2022 International Symposium on Nonlinear Theory and Its Applications (NOLTA2022)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Presentation] Design of a Low-Power FPGA-Based CNN Accelerator Based on Nonvolatile Logic-in-Memory Circuitry2022

    • Author(s)
      D. Suzuki, M. Natsui, A. Tamakoshi, Y. Takako, and T. Hanyu
    • Organizer
      2022 International Symposium on Nonlinear Theory and Its Applications (NOLTA 2022)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-21H04868
  • [Presentation] Dynamic Power-Gating-Switch Control Technique and Its Application to an Energy-Efficient Embedded STT-MRAM2021

    • Author(s)
      F. Zhong, M. Natsui, and T. Hanyu
    • Organizer
      2021 International Conference on Solid State Devices and Materials (SSDM2021)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Presentation] 次世代エッジコンピューティングを支える集積回路技術2021

    • Author(s)
      夏井雅典
    • Organizer
      電子情報通信学会東北支部学術講演会
    • Invited
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Presentation] K.C.Smith賞受賞時の研究とその後の研究の展望について ~不揮発ロジックインメモリ構造を活用したポストプロセスばらつき補正技術とその応用展開~2021

    • Author(s)
      夏井雅典
    • Organizer
      第44回多値論理フォーラム
    • Invited
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] Dynamic Power-Gating-Switch Control Technique and Its Application to an Energy-Efficient Embedded STT-MRAM2021

    • Author(s)
      F. Zhong, M. Natsui, and T. Hanyu
    • Organizer
      2021 International Conference on Solid State Devices and Materials (SSDM2021)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] 次世代エッジコンピューティングを支える集積回路技術2021

    • Author(s)
      夏井雅典
    • Organizer
      電子情報通信学会東北支部学術講演会
    • Invited
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] 磁気トンネル接合素子を活用した高性能・省エネルギー不揮発LSIの開発2021

    • Author(s)
      夏井雅典
    • Organizer
      R025先進薄膜界面機能創成委員会 第6回研究会
    • Invited
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] Power-Gating Switch-Control Technique for Nonvolatile Logic LSI2021

    • Author(s)
      F. Zhong, M. Natsui, and T. Hanyu
    • Organizer
      The 4th Symposium for The Core Research Clusters for Materials Science and Spintronics
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage2021

    • Author(s)
      夏井雅典
    • Organizer
      集積回路研究会「メモリ技術と集積回路技術一般」
    • Invited
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Presentation] Dynamic Power-Gating-Switch Control Technique and Its Application to an Energy-Efficient Embedded STT-MRAM2021

    • Author(s)
      Fangcen Zhong, Masanori Natsui, and Takahiro Hanyu
    • Organizer
      2021 International Conference on Solid State Devices and Materials (SSDM)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-21H04868
  • [Presentation] K.C.Smith賞受賞時の研究とその後の研究の展望について ~不揮発ロジックインメモリ構造を活用したポストプロセスばらつき補正技術とその応用展開~2021

    • Author(s)
      夏井雅典
    • Organizer
      第44回多値論理フォーラム
    • Invited
    • Data Source
      KAKENHI-PROJECT-23K21651
  • [Presentation] 動作環境適応型パワーゲーティングスイッチ制御技術とその不揮発ロジックLSIへの応用2021

    • Author(s)
      鐘方岑,夏井雅典,羽生貴弘
    • Organizer
      デザインガイア2021 -VLSI設計の新しい大地-
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] Impact of nonvolatile-logic design techniques for spintronics-based edge AI computing2020

    • Author(s)
      M. Natsui, T. Chiba and T. Hanyu
    • Organizer
      The 8th RIEC International Symposium on Brain Functions and Brain Computer
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] Design of a Magnetic-Tunnel-Junction-Based Nonvolatile Flip-Flop with Common-Mode Write Error Detection2020

    • Author(s)
      G. Yamagishi, M. Natsui, and T. Hanyu
    • Organizer
      2020 International Conference on Solid State Devices and Materials
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] 不揮発ロジックLSIのパワーゲーティングスイッチ制御技術に関する一検討2020

    • Author(s)
      鐘方岑,夏井雅典,羽生貴弘
    • Organizer
      デザインガイア2020 -VLSI設計の新しい大地-
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] Design of a Resilient Nonvolatile Flip-Flop with Common-Mode Write Error Detection2020

    • Author(s)
      G. Yamagishi, M. Natsui, and T. Hanyu
    • Organizer
      The 3rd Symposium for The Core Research Clusters for Materials Science and Spintronics
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] 非相補抵抗状態検出機能を有する高信頼MTJベース不揮発性フリップフロップの構成2019

    • Author(s)
      山岸源征,夏井雅典,羽生貴弘
    • Organizer
      令和元年度電気関係学会東北支部連合大会
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] Nonvolatile Logic LSI Design Technology and Its Application to AI Hardware2019

    • Author(s)
      M. Natsui
    • Organizer
      2019 International Conference on Solid State Devices and Materials (SSDM2019)
    • Invited / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] Impact of MTJ-Based Nonvolatile Microcontroller LSI for IoT Applications2019

    • Author(s)
      M. Natsui, D. Suzuki, A. Tamakoshi, H. Sato, S. Ikeda, T. Endoh, and T. Hanyu
    • Organizer
      5th CIES Technology Forum / DAY 1 International Symposium
    • Invited / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] MTJ-Based Nonvolatile Logic Gates for Quantized Neural Network Hardware2019

    • Author(s)
      M. Natsui, T. Chiba and T. Hanyu
    • Organizer
      The 6th International Symposium on Brainware LSI
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Presentation] An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJHybrid Technology Achieving 47.14μW Operation at 200MHz2019

    • Author(s)
      M. Natsui, D. Suzuki, A. Tamakoshi, T. Watanabe, H. Honjo, H. Koike, T. Nasuno, Y. Ma, T. Tanigawa, Y. Noguchi, M. Yasuhira, H. Sato, S. Ikeda, H. Ohno, T. Endoh, and T. Hanyu
    • Organizer
      2019 IEEE International Solid-State Circuits Conference (ISSCC2019)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJHybrid Technology Achieving 47.14μW Operation at 200MHz2019

    • Author(s)
      M. Natsui, D. Suzuki, A. Tamakoshi, T. Watanabe, H. Honjo, H. Koike, T. Nasuno, Y. Ma, T. Tanigawa, Y. Noguchi, M. Yasuhira, H. Sato, S. Ikeda, H. Ohno, T. Endoh, and T. Hanyu
    • Organizer
      2019 IEEE International Solid-State Circuits Conference (ISSCC2019)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Presentation] MTJベースばらつき補正機能を用いた2値化ニューラルネットワーク向け低消費電力・省面積bitcount回路の構成2019

    • Author(s)
      千葉智貴,夏井雅典,羽生貴弘
    • Organizer
      第32回多値論理とその応用研究会
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] Design of a Current-Mode Linear-Sum-Based Bitcounting Circuit with an MTJ-Based Compensator for Binarized Neural Networks2019

    • Author(s)
      T. Chiba, M. Natsui and T. Hanyu
    • Organizer
      49th IEEE International Symposium on Multiple-Valued Logic (ISMVL2019)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] Impact of MTJ-Based Nonvolatile Microcontroller LSI for IoT Applications2019

    • Author(s)
      M. Natsui, D. Suzuki, A. Tamakoshi, H. Sato, S. Ikeda, T. Endoh, and T. Hanyu
    • Organizer
      5th CIES Technology Forum / DAY 1 International Symposium
    • Invited / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Presentation] 省エネルギー二値化ニューラルネットワーク向けMTJベース積和演算回路の構成2019

    • Author(s)
      千葉智貴,夏井雅典,羽生貴弘
    • Organizer
      デザインガイア2019 -VLSI設計の新しい大地-
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] MTJ-Based Nonvolatile Logic Gates for Quantized Neural Network Hardware2019

    • Author(s)
      M. Natsui, T. Chiba and T. Hanyu
    • Organizer
      The 6th International Symposium on Brainware LSI
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJHybrid Technology Achieving 47.14μW Operation at 200MHz2019

    • Author(s)
      M. Natsui
    • Organizer
      IEEE SSCS Kansai Chapter Technical Seminar
    • Invited
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Presentation] Design of an MTJ-Based Fully-Nonvolatile Microcontroller LSI and Its Impact on IoT Applications2019

    • Author(s)
      M. Natsui and T. Hanyu
    • Organizer
      28th International Workshop on Post-Binary ULSI Systems
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJHybrid Technology Achieving 47.14μW Operation at 200MHz2019

    • Author(s)
      M. Natsui
    • Organizer
      IEEE SSCS Kansai Chapter Technical Seminar
    • Invited
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] MTJ-Based Nonvolatile Logic-in-Memory Circuit with Feedback-Type Equal-Resistance Sensing Mechanism for Ternary Neural Network Hardware2019

    • Author(s)
      M. Natsui and T. Hanyu
    • Organizer
      IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] MTJベースばらつき補正機能を用いた2値化ニューラルネットワーク向け低消費電力・省面積bitcount回路の構成2018

    • Author(s)
      千葉智貴,夏井雅典,羽生貴弘
    • Organizer
      第32回多値論理とその応用研究会
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Presentation] MTJ-Based Nonvolatile Logic Gate for Binarized Convolutional Neural Networks and Its Impact2018

    • Author(s)
      M. Natsui, T. Chiba and T. Hanyu
    • Organizer
      2018 International Conference on Solid State Devices and Materials (SSDM2018)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Presentation] 次世代IoT社会に向けた脳型LSI設計技術2018

    • Author(s)
      夏井雅典
    • Organizer
      電子情報通信学会 総合大会
    • Invited
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Presentation] 脳型計算に基づく非シグネチャ不正侵入検出手法2018

    • Author(s)
      須田拓樹,夏井雅典,羽生貴弘
    • Organizer
      第31回多値論理とその応用研究会
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Presentation] MTJ-Based Nonvolatile Logic Gate for Binarized Convolutional Neural Networks and Its Impact2018

    • Author(s)
      M. Natsui, T. Chiba and T. Hanyu
    • Organizer
      2018 International Conference on Solid State Devices and Materials (SSDM2018)
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] 不揮発量子化ニューラルネットワーク構造に基づく小型・超低消費電力XNOR回路の構成2018

    • Author(s)
      千葉智貴,夏井雅典,羽生貴弘
    • Organizer
      平成30年度電気関係学会東北支部連合大会
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Presentation] MTJ-Based Nonvolatile Logic LSI for Ultra Low-Power and Highly Dependable Computing2018

    • Author(s)
      M. Natsui, T. Endoh, H. Ohno, and T. Hanyu
    • Organizer
      China Semiconductor Technology International Conference (CSTIC)
    • Invited / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Presentation] スピントロニクスが拓く新しいロジックLSIの展望2018

    • Author(s)
      羽生貴弘,鈴木大輔,鬼沢直哉,夏井雅典,遠藤哲郎,大野英男
    • Organizer
      CSRN年度末シンポジウム
    • Invited
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Presentation] MTJ-Based Nonvolatile Ternary Logic Gate for Quantized Convolutional Neural Networks2018

    • Author(s)
      M. Natsui, T. Chiba and T. Hanyu
    • Organizer
      IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] MTJ-Based Nonvolatile Ternary Logic Gate for Quantized Convolutional Neural Networks2018

    • Author(s)
      M. Natsui, T. Chiba and T. Hanyu
    • Organizer
      IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Presentation] Data-Stream-Aware Computing for Highly Dependable VLSI Systems2018

    • Author(s)
      M. Natsui, H. Suda and T. Hanyu
    • Organizer
      The 5th International Symposium on Brainware LSI
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Presentation] 不揮発量子化ニューラルネットワーク構造に基づく小型・超低消費電力XNOR回路の構成2018

    • Author(s)
      千葉智貴,夏井雅典,羽生貴弘
    • Organizer
      平成30年度電気関係学会東北支部連合大会
    • Data Source
      KAKENHI-PROJECT-17KK0001
  • [Presentation] Systematic Intrusion Detection Technique for In-Vehicle Network Based on Time-Series Feature Extraction2018

    • Author(s)
      H. Suda, M. Natsui, and T. Hanyu
    • Organizer
      48th IEEE International Symposium on Multiple-Valued Logic (ISMVL2018)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Presentation] Three-Terminal MTJ-Based Nonvolatile Logic Circuits with Self-Terminated Writing Mechanism for Ultra-Low-Power VLSI Processor2017

    • Author(s)
      T. Hanyu, D. Suzuki, N. Onizawa, and M. Natsui
    • Organizer
      Design, Automation & Test in Europe (DATE)
    • Invited / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Presentation] 時系列特徴を用いた脳型計算ベース車載ネットワークセキュリティ技術2017

    • Author(s)
      夏井雅典,須田拓樹,羽生貴弘
    • Organizer
      多値論理研究ノート
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Presentation] Energy-Efficient Data-Access Technique for an Ultra Low-Power Nonvolatile Microcontroller Unit2017

    • Author(s)
      M. Natsui and T. Hanyu
    • Organizer
      3rd ImPACT International Symposium on Spintronic Memory, Circuit and Storage
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Presentation] 脳型LSIを拓く集積回路・アーキテクチャの展望2017

    • Author(s)
      夏井雅典
    • Organizer
      VLSI夏の学校「LSI技術者のための人工知能基礎講座」
    • Invited
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Presentation] 時系列特徴を用いたチップ内データ転送エラー訂正手法とその可能性2017

    • Author(s)
      加藤健太郎,夏井雅典,羽生貴弘
    • Organizer
      デザインガイア2017 -VLSI設計の新しい大地-
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Presentation] 脳型計算に基づく車載ネットワークの不正侵入検出法2017

    • Author(s)
      須田拓樹,夏井雅典,羽生貴弘
    • Organizer
      平成29年度電気関係学会東北支部連合大会
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Presentation] Energy-Efficient High-Performance Nonvolatile VLSI Processor with a Temporary-Data Reuse Technique2017

    • Author(s)
      M. Natsui and T. Hanyu
    • Organizer
      Extended Abstracts of 2017 International Conference on Solid State Devices and Materials (SSDM2017)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Presentation] 適切な通信ネットワークのトラフィックを考慮した高機能・低コストエッジプロセッサの構成に関する一考察2017

    • Author(s)
      加藤健太郎,夏井雅典,羽生貴弘
    • Organizer
      第30回多値論理とその応用研究会
    • Place of Presentation
      石川県金沢市
    • Year and Date
      2017-01-07
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Presentation] 時系列特徴を考慮した脳型計算ベース車載ネットワークセキュリティ技術に関する基礎的検討2017

    • Author(s)
      須田拓樹,夏井雅典,羽生貴弘
    • Organizer
      LSIとシステムのワークショップ2017
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Presentation] Towards Ultra Low-Power and Highly Dependable VLSI Computing Based on MTJ-Based Nonvolatile Logic-in-Memory Architecture2016

    • Author(s)
      M. Natsui, T. Endoh, H. Ohno, and T. Hanyu
    • Organizer
      BIT's 6th Annual World Congress of Nano Science & Technology 2016
    • Place of Presentation
      シンガポール
    • Year and Date
      2016-10-26
    • Invited / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Presentation] Highly Reliable MTJ-Based Nonvolatile Logic-in-Memory LSI with Content-Aware Write Error Masking Scheme2016

    • Author(s)
      M. Natsui, A. Tamakoshi, T. Endoh, H. Ohno, and T. Hanyu
    • Organizer
      2016 International Conference on Solid State Devices and Materials
    • Place of Presentation
      茨城県つくば市
    • Year and Date
      2016-09-26
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16KT0187
  • [Presentation] Highly Reliable MTJ-Based Motion-Vector Prediction Unit with Dynamic Write Error Masking Scheme2016

    • Author(s)
      Masanori Natsui, Akira Tamakoshi, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu
    • Organizer
      2016 International Conference on Solid State Devices and Materials (SSDM2016)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Presentation] MTJ/MOS-Hybrid Logic-Circuit Design Flow for Nonvolatile Logic-in-Memory LSI2013

    • Author(s)
      M. Natsui, N. Sakimura, T. Sugibayashi, and T, Hanyu
    • Organizer
      2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)
    • Place of Presentation
      Beijing, China
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] MTJ素子を用いた不揮発ロジックLSIの低電力化に関する一考察2013

    • Author(s)
      夏井雅典, 荒木敦司, 羽生貴弘
    • Organizer
      多値論理研究ノート
    • Place of Presentation
      兵庫
    • Year and Date
      2013-09-14
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] MTJ 素子を用いた不揮発ロジックLSI の低電力化に関する一考察2013

    • Author(s)
      夏井雅典,荒木敦司,羽生貴弘
    • Organizer
      第36回多値論理フォーラム
    • Place of Presentation
      姫路
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Design of a Low-Voltage Logic Gate Based on Differential-Pair Circuitry2013

    • Author(s)
      K. Kashiuchi, M. Natsui, and T. Hanyu
    • Organizer
      2013 International Workshop on Emerging ICT
    • Place of Presentation
      Sendai, Japan
    • Year and Date
      2013-10-29
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Design and Evaluation of a Differential Switching Gate for Low-Voltage Applications2013

    • Author(s)
      M. Natsui, K. Kashiuchi, and T. Hanyu
    • Organizer
      43rd IEEE International Symposium on Multiple-Valued Logic (ISMVL2013)
    • Place of Presentation
      Toyama, Japan
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Design of an MTJ-Based Variation-Resilient Basic Gate of Differential Logic2012

    • Author(s)
      Y. Kim, M. Natsui and T. Hanyu
    • Organizer
      平成24年度電気関係学会東北支部連合大会
    • Place of Presentation
      秋田
    • Year and Date
      2012-08-30
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Vth補償機能を有するMOS/MTJハイブリッド電流モードロジックとその最適化2012

    • Author(s)
      キム ヨンクン, 夏井雅典, 羽生貴弘
    • Organizer
      第25回多値論理とその応用研究会
    • Place of Presentation
      宮崎観光ホテル
    • Year and Date
      2012-01-08
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] 低電圧動作差動論理基本ゲートの構成に関する一考察2012

    • Author(s)
      樫内清弘, 夏井雅典, 羽生貴弘
    • Organizer
      多値論理研究ノート
    • Place of Presentation
      富山
    • Year and Date
      2012-09-15
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Fundamental Technologies of High-Performance VLSI Processor for Multimedia Applications2012

    • Author(s)
      T.Hanyu, M.Natsui, A.Matsumoto
    • Organizer
      The 5th International Symposium and The 4th Student-Organizing International Mini-Conference on Information Electronics Systems
    • Place of Presentation
      仙台ウエスティンホテル
    • Year and Date
      2012-02-23
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Vth補償機能を有するMOS/MTJハイブリッド電流モードロジックとその最適化2012

    • Author(s)
      キムヨンクン, 夏井雅典, 羽生貴弘
    • Organizer
      第25回多値論理とその応用研究会
    • Place of Presentation
      宮崎
    • Year and Date
      2012-01-08
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] 低スイッチング電力基本論理ゲートの構成に関する一考察2012

    • Author(s)
      樫内清弘, 夏井雅典, 羽生貴弘
    • Organizer
      平成24年度電気関係学会東北支部連合大会
    • Place of Presentation
      秋田
    • Year and Date
      2012-08-30
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Vth補償機能を有するMOS/MTJハイブリッド電流モードロジックとその最適化2012

    • Author(s)
      キムヨンクン, 夏井雅典, 羽生貴弘
    • Organizer
      第25回多値論理とその応用研究会
    • Place of Presentation
      宮崎観光ホテル
    • Year and Date
      2012-01-08
    • Data Source
      KAKENHI-PROJECT-21700051
  • [Presentation] 可変抵抗素子を用いたポストプロセスばらつき補償機能付きOTAの検討2011

    • Author(s)
      長嶋孝晃, 夏井雅典, 桝井昇一, 羽生貴弘
    • Organizer
      平成23年度電気関係学会東北支部連合大会
    • Place of Presentation
      宮城
    • Year and Date
      2011-08-26
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] 不揮発性ロジックインメモリアーキテクチャに基づく高信頼VLSI設計技術2011

    • Author(s)
      夏井雅典, 羽生貴弘
    • Organizer
      第73回ニューパラダイムコンピューティング研究会
    • Place of Presentation
      会津大学
    • Year and Date
      2011-07-30
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] 不揮発性可変抵抗素子を用いたLSIパラメータばらつき最小化アルゴリズムの検討2011

    • Author(s)
      キム ヨンクン, 夏井雅典, 羽生貴弘
    • Organizer
      平成23年度電気関係学会東北支部連合大会
    • Place of Presentation
      東北学院大学
    • Year and Date
      2011-08-26
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] 不揮発性ロジックインメモリアーキテクチャが拓く新概念VLSI設計パラダイム2011

    • Author(s)
      夏井雅典, 羽生貴弘
    • Organizer
      LSIとシステムのワークショップ2011
    • Place of Presentation
      北九州国際会議場
    • Year and Date
      2011-05-16
    • Data Source
      KAKENHI-PROJECT-21700051
  • [Presentation] Evaluation of Vth-Variation Effect on Multiple-Valued Current-Mode Circuits2011

    • Author(s)
      K. Kashiuchi, M. Natsui, and T. Hanyu
    • Organizer
      Proceedings of 2011 China-Korea-Japan Electronics and Communications Conference
    • Place of Presentation
      University of Electronic Science and Technology of China, China
    • Year and Date
      2011-10-27
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] MTJ素子を用いた完全並列形不揮発TCAMワード回路の構成2011

    • Author(s)
      勝俣翠, 松永翔雲, 夏井雅典, 羽生貴弘
    • Organizer
      第24回多値論理とその応用研究会
    • Place of Presentation
      東北大学
    • Year and Date
      2011-01-08
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] 不揮発性ロジックインメモリアーキテクチャが拓く新概念VLSI設計パラダイム2011

    • Author(s)
      夏井雅典, 羽生貴弘
    • Organizer
      LSIとシステムのワークショップ2011
    • Place of Presentation
      北九州国際会議場
    • Year and Date
      2011-05-16
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Evaluation of Vth-Variation Effect on Multiple-Valued Current-Mode Circuits2011

    • Author(s)
      K.Kashiuchi, M.Natsui, T.Hanyu
    • Organizer
      2011 China-Korea-Japan Electronics and Communications Conference
    • Place of Presentation
      中国,成都
    • Year and Date
      2011-10-27
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] 不揮発性ロジックインメモリアーキテクチャに基づく高信頼VLSI設計技術2011

    • Author(s)
      夏井雅典, 羽生貴弘
    • Organizer
      第73回ニューパラダイムコンピューティング研究会
    • Place of Presentation
      会津大学
    • Year and Date
      2011-07-30
    • Data Source
      KAKENHI-PROJECT-21700051
  • [Presentation] 不揮発性ロジックインメモリアーキテクチャが拓く新コンピューティングパラダイムの展望2011

    • Author(s)
      夏井雅典, 羽生貴弘
    • Organizer
      第58回応用物理学関係連合講演会
    • Place of Presentation
      神奈川工科大学
    • Year and Date
      2011-03-24
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] 不揮発性ロジックインメモリアーキテクチャが拓く新概念VLSI 設計パラダイム2011

    • Author(s)
      夏井雅典, 羽生貴弘
    • Organizer
      LSI とシステムのワークショップ2011
    • Place of Presentation
      福岡
    • Year and Date
      2011-05-16
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] 不揮発性可変抵抗素子を用いたLSIパラメータばらつき最小化アルゴリズムの検討2011

    • Author(s)
      キムヨンクン, 夏井雅典, 羽生貴弘
    • Organizer
      平成23年度電気関係学会東北支部連合大会
    • Place of Presentation
      東北学院大学
    • Year and Date
      2011-08-26
    • Data Source
      KAKENHI-PROJECT-21700051
  • [Presentation] 不揮発性可変抵抗素子を用いたLSIパラメータばらつき最小化アルゴリズムの検討2011

    • Author(s)
      キムヨンクン, 夏井雅典, 羽生貴弘
    • Organizer
      平成23年度電気関係学会東北支部連合大会
    • Place of Presentation
      宮城
    • Year and Date
      2011-08-26
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] 可変抵抗素子を用いたポストプロセスばらつき補償機能付きOTAの検討2011

    • Author(s)
      長嶋孝晃, 夏井雅典, 桝井昇一, 羽生貴弘
    • Organizer
      平成23年度電気関係学会東北支部連合大会
    • Place of Presentation
      東北学院大学
    • Year and Date
      2011-08-26
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] MTJ素子を用いた完全並列形不揮発TCAMワード回路の構成2011

    • Author(s)
      勝俣翠, 松永翔雲, 夏井雅典, 羽生貴弘
    • Organizer
      第24回多値論理とその応用研究会
    • Place of Presentation
      宮城
    • Year and Date
      2011-01-08
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Low-Energy Pipelined Multiple-Valued Current-Mode Circuit with 8-Level Static Current-Source Control2010

    • Author(s)
      Masanori Natsui
    • Organizer
      40th IEEE International Symposium on Multiple-Valued Logic
    • Place of Presentation
      Casa Convalescencia(バルセロナ,スペイン)
    • Year and Date
      2010-05-26
    • Data Source
      KAKENHI-PROJECT-21700051
  • [Presentation] Process-Variation-Aware VLSI Design Using Emerging Functional Devices and Its Impact2010

    • Author(s)
      Masanori Natsui
    • Organizer
      19th International Workshop on Post-Binary ULSI Systems
    • Place of Presentation
      Casa Convalescencia(バルセロナ,スペイン)
    • Year and Date
      2010-05-25
    • Data Source
      KAKENHI-PROJECT-21700051
  • [Presentation] MTJ-Based Nonvolatile Reconfigurable LSI with Fine Grained Power Management2010

    • Author(s)
      L.Yuhui, D.Suzuki, M.Natsui, T.Hanyu
    • Organizer
      Japan-China-Korea Conference on Electronics & Communications 2010
    • Place of Presentation
      東北大学
    • Year and Date
      2010-11-01
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Design of a Dependable Logic Circuit Using Nonvolatile Programmable Devices2010

    • Author(s)
      Y. Kim, M. Natsui and T. Hanyu
    • Organizer
      Japan-China-Korea Conference on Electronics & Communications 2010
    • Place of Presentation
      Tohoku University, Sendai, Japan
    • Year and Date
      2010-11-01
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Fundamental Technologies towards New Paradigm VLSI Computing2010

    • Author(s)
      T.Hanyu, M.Natsui, A.Matsumoto, S.Matsunaga, N.Onizawa, D.Suzuki
    • Organizer
      The 4th International Symposium on Information Electronics Systems
    • Place of Presentation
      仙台エクセルホテル東急
    • Year and Date
      2010-07-08
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] 完全並列形不揮発TCAM向けワード回路の構成2010

    • Author(s)
      勝俣翠, 松永翔雲, 夏井雅典, 羽生貴弘
    • Organizer
      平成22年度電気関係学会東北支部連合大会
    • Place of Presentation
      八戸工業大学
    • Year and Date
      2010-08-26
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Process-Variation-Aware VLSI Design Using an Emerging Functional Devices and Its Impact2010

    • Author(s)
      M.Natsui, T.Hanyu
    • Organizer
      19th International Workshop on Post-Binary ULSI Systems
    • Place of Presentation
      スペイン,バルセロナ
    • Year and Date
      2010-05-28
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] MTJ-Based Nonvolatile Reconfigurable LSI with Fine Grained Power Management2010

    • Author(s)
      L. Yuhui, D. Suzuki, M. Natsui and T. Hanyu
    • Organizer
      Japan-China-Korea Conference on Electronics & Communications 2010
    • Place of Presentation
      Tohoku University, Sendai, Japan
    • Year and Date
      2010-11-01
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] High-yield VLSI design using emerging functional devices and its impact2010

    • Author(s)
      M.Natsui
    • Organizer
      2010 Joint Workshop between Tohoku University and National Tsing Hua University
    • Place of Presentation
      仙台秋保温泉佐勘
    • Year and Date
      2010-12-15
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] ポストプロセスばらつき補償形回路アーキテクチャの一検討2010

    • Author(s)
      夏井雅典, 羽生貴弘
    • Organizer
      第23回多値論理とその応用研究会
    • Place of Presentation
      明治大学
    • Year and Date
      2010-01-09
    • Data Source
      KAKENHI-PROJECT-21700051
  • [Presentation] MTJ素子を用いた低消費電力不揮発性TCAMのパワーゲーティング手法2010

    • Author(s)
      松永翔雲, 夏井雅典, 羽生貴弘
    • Organizer
      多値論理研究ノート
    • Place of Presentation
      広島
    • Year and Date
      2010-09-11
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] High-yield VLSI design using emerging functional devices and its impact2010

    • Author(s)
      M. Natsui
    • Organizer
      2010 Joint Workshop between Tohoku University and National Tsing Hua University
    • Place of Presentation
      Akiu Resort Hotel Sakan, Sendai, Japan
    • Year and Date
      2010-12-15
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] 適応的電流制御に基づく低電力パイプライン形多値電流モード回路の構成2010

    • Author(s)
      有光貴志, 夏井雅典, 羽生貴弘
    • Organizer
      第23回多値論理とその応用研究会
    • Place of Presentation
      明治大学
    • Year and Date
      2010-01-09
    • Data Source
      KAKENHI-PROJECT-21700051
  • [Presentation] MTJ素子を用いた低消費電力不揮発性TCAMのパワーケーディング手法2010

    • Author(s)
      松永翔雲, 夏井雅典, 羽生貴弘
    • Organizer
      第33回多値論理フォーラム
    • Place of Presentation
      広島市まちづくり市民交流プラザ
    • Year and Date
      2010-09-11
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Design of a Dependable Logic Circuit Using Nonvolatile Programmable Devices2010

    • Author(s)
      Y.Kim, M.Natsui, T.Hanyu
    • Organizer
      Japan-China-Korea Conference on Electronics & Communications 2010
    • Place of Presentation
      東北大学
    • Year and Date
      2010-11-01
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] ポストプロセスばらつき補償形回路アーキテクチャの一検討2010

    • Author(s)
      夏井雅典
    • Organizer
      第23回多値論理とその応用研究会
    • Place of Presentation
      明治大学(東京都)
    • Year and Date
      2010-01-09
    • Data Source
      KAKENHI-PROJECT-21700051
  • [Presentation] 完全並列形不揮発TCAM向けワード回路の構成2010

    • Author(s)
      勝俣翠, 松永翔雲, 夏井雅典, 羽生貴弘
    • Organizer
      平成22年度電気関係学会東北支部連合大会
    • Place of Presentation
      青森
    • Year and Date
      2010-08-26
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Process-Variation-Aware VLSI Design Using an Emerging Functional Devices and Its Impact2010

    • Author(s)
      M. Natsui and T. Hanyu
    • Organizer
      Booklet of the 19th International Workshop on Post-Binary ULSI Systems
    • Place of Presentation
      Casa Convalescencia, Barcelona, Spain
    • Year and Date
      2010-05-28
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] 二次元LUTを用いた電流モード多値回路向け高速・高精度動作検証手法の一考察2009

    • Author(s)
      有光貴志, 夏井雅典, 羽生貴弘
    • Organizer
      平成21年度電気関係学会東北支部連合大会
    • Place of Presentation
      東北文化学園大学
    • Year and Date
      2009-08-20
    • Data Source
      KAKENHI-PROJECT-21700051
  • [Presentation] Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System2009

    • Author(s)
      T. Matsuura, H. Shirahama, M. Natsui and T. Hanyu
    • Organizer
      Naha
    • Place of Presentation
      Okinawa, Japan
    • Year and Date
      2009-05-21
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] MOS/MTJ-Hybrid Circuit with Nonvolatile Logic-in-Memory Architecture2009

    • Author(s)
      夏井雅典
    • Organizer
      2009 International Conference on Solid State Devices and Materials(SSDM2009)
    • Place of Presentation
      東北大学(仙台市)
    • Year and Date
      2009-10-06
    • Data Source
      KAKENHI-PROJECT-21700051
  • [Presentation] MOS/MTJ-Hybrid Circuit with Nonvolatile Logic-in-Memory Architecture2009

    • Author(s)
      M. Natsui and T. Hanyu
    • Organizer
      2009 International Conference on Solid State Devices and Materials (SSDM2009)
    • Place of Presentation
      東北大学
    • Year and Date
      2009-10-06
    • Data Source
      KAKENHI-PROJECT-21700051
  • [Presentation] 出力状態モニタリングに基づく電流モード多値順序回路の低消費電力化2008

    • Author(s)
      松浦貴史, 白濱弘勝, 夏井雅典, 羽生貴弘
    • Organizer
      第31回多値論理フォーラム
    • Place of Presentation
      沖縄
    • Year and Date
      2008-09-12
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 適応的電流源制御に基づくパイプライン電流モード多値演算回路の低電力化2008

    • Author(s)
      松浦貴史, 白濱弘勝, 夏井雅典, 羽生貴弘
    • Place of Presentation
      沖縄
    • Year and Date
      2008-09-12
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Systematic Design and Verification of Binary / Multiple-V alued Fused Logic Circuits2008

    • Author(s)
      Takashi Arimitsu, Tasuku Nagai, Masanori Natsui and Takahiro Hanyu
    • Organizer
      Proceedings of 2008 China-Korea-Japan Graduates Workshop on Electronic Information
    • Place of Presentation
      成都(中国)
    • Year and Date
      2008-10-30
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 次世代VLSI向き多値回路の系統的設計2008

    • Author(s)
      夏井雅典, 羽生貴弘
    • Place of Presentation
      沖縄
    • Year and Date
      2008-09-12
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Systematic Design and Verification of Binary/Multiple-Valued Fused Logic Circuits2008

    • Author(s)
      T. Arimitsu, T. Nagai, M. Natsui and T. Hanyu
    • Place of Presentation
      Chengdu, China
    • Year and Date
      2008-10-30
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 出力状態モニタリングに基づく電流モード多値順序回路の低消費電力化2008

    • Author(s)
      松浦貴史, 白濱弘勝, 夏井雅典, 羽生貴弘
    • Organizer
      平成20年度電気関係学会東北支部連合大会講演論文集
    • Place of Presentation
      郡山
    • Year and Date
      2008-08-22
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 出力状態モニタリングに基づく電流モード多値順序回路の低消費電力化2008

    • Author(s)
      松浦貴史, 白濱弘勝, 夏井雅典, 羽生貴弘
    • Place of Presentation
      福島
    • Year and Date
      2008-08-22
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Pitch estimation of polyphony having many musical tones using seven comb filters connected in cascade2007

    • Author(s)
      Y.Tadokoro, D.Matsuyama and M.Natsui
    • Organizer
      International Workshop on Nonlinear Signal and Image Processing
    • Place of Presentation
      Bucharest, Romania
    • Year and Date
      2007-09-11
    • Data Source
      KAKENHI-PROJECT-19500082
  • [Presentation] 主成分分析によるGAの探索効率化と低電圧型カレントミラー回路のパラメータ最適化への応用2007

    • Author(s)
      夏井雅典
    • Organizer
      平成19年度電気関係学会東海支部連合大会
    • Place of Presentation
      信州大学
    • Year and Date
      2007-09-28
    • Data Source
      KAKENHI-PROJECT-18700044
  • 1.  HANYU Takahiro (40192702)
    # of Collaborated Projects: 6 results
    # of Collaborated Products: 113 results
  • 2.  米田 友洋 (30182851)
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 0 results
  • 3.  今井 雅 (70323665)
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 0 results
  • 4.  MOCHIZUKI Akira (40359542)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 5.  MATSUMOTO Atsushi (40455853)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 6.  TADOKORO Yoshiaki (90005463)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 1 results
  • 7.  SAITOU Tutomu (60280393)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 8.  KUDOU Norimasa (40270194)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 9.  NOGUCHI Kenntarou (00335100)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 10.  YAMAGUCHI Michiru (60413762)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 11.  池田 正二 (90281865)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 2 results
  • 12.  鬼沢 直哉 (90551557)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 3 results
  • 13.  村口 正和 (90386623)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results

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