HANYU Takahiro 羽生貴弘

… Alternative Names

Hanyu Takahiro 羽生貴弘

HANYU TAKAHIRO 羽生貴弘

羽生貴広ハニュウタカヒロ

Less

Researcher Number	40192702
Other IDs
External Links
Affiliation (Current)	2025: 東北大学, 電気通信研究所, 教授
Affiliation (based on the past Project Information) *help	2015 – 2024: 東北大学, 電気通信研究所, 教授 2010 – 2013: 東北大学, 電気通信研究所, 教授 2002 – 2008: Tohoku University, Research Institute of Electrical Communication, Professor, 電気通信研究所, 教授 1993 – 2001: 東北大学, 大学院・情報科学研究科, 助教授 1998: 東北大学, 大学院・情報科学研究所, 助教授 … More 1996 – 1997: Tohoku University, Graduate School of Information Sciences, Associate Professor, 大学院情報科学研究科, 助教授 1993: Tohoku University, Graduate school of Information Sciences, 情報科学研究科, 助教授 1992: TOHOKU UNIVERSITY FACULTY OF ENGINEERING ASSOCIATE PROFESSOR, 工学部, 助教授 1989 – 1991: 東北大学, 工学部, 助手 Less
Review Section/Research Field	Principal Investigator 計算機科学 / Computer system/Network / Computer system / Medium-sized Section 60:Information science, computer engineering, and related fields / Electron device/Electronic equipment / 計測・制御工学 Except Principal Investigator 計算機科学 / Basic Section 60040:Computer system-related / 計測・制御工学 / Communication/Network engineering / 計測・制御工学
Keywords	Principal Investigator 不揮発性ロジック / フローティングゲートMOSトランジスタ / 非同期式回路 / 非数値データ処理 / 超並列処理 / 情報システム / しきい演算 / 大小比較演算 / 多値連想メモリ / 脳型ハードウェア … More / 計算機システム / 知的情報処理 / ロジックインメモリ構造 / 情報通信工学 / 記憶・演算一体化 / セルフチェッキング回路 / 差動対回路 / 電流線形加算 / ばらつき補正機能 / はらつき補正機能 / MTJデバイス / ロジックLSI / 高速・低電力回路技術 / ダイ・ハード回路 / IoT応用 / ダーク・シリコンLSI / CMOS/MTJハイブリッド回路 / 不揮発ロジック / 脳型情報処理 / multiple-valued encoding / intra-chip high-speed signaling / network-on-chip / system-on-chip / semiconductor ultra-scaling / equipments / electronic devices / information communication engineering / information system / デュプレックス / プロトコル / 2線式 / チップ内通信 / 双方向同時通信 / 非同期通信プロトコル / 2線符号化方式 / クロックスキュー / クロック分配 / ハンドシェイク通信 / 多値符号化 / チップ内高速データ転送技術 / ネットワークオンチップ / システムオンチップ / 半導体超微細化 / 電子デバイス・機器 / data-transfer bottleneck / operation merging / storage / resistor-circuit network / device modeling / fully parallel processing / ferroelectric capacitor / TMR device / multiple-valued logic-in-memory / 多値基本演算子 / マイクロ順序動作 / ゲートレベルパイプライン処理 / パイプライン乗算器 / 多値集積回路 / ゲートレベルパイプライン / FPGA / 強誘電体CAM / 相補的動作 / 非破壊読出し / デバイスモデル / 全加算器 / 強誘電体デバイス / データ転送ボトルネックフリー / 抵抗回路網 / デバイスモデリング / 超並列演算 / 強誘電体キャパシタ / TMR素子 / 多値ロジックインメモリ / Dual-Rail Current-Mode Circuit / Current-to-Voltage Converter / Current-Mode Linear Sum / Output Generator / Current-Mode Comparator / Current-Mirror-less Circuit / Differential-Pair Circuit / Multiple-Valued Current-Mode Circuit / 算術演算回路 / 2進SD数表現 / 線形加算回路 / スレッショルドディテクタ / 2線式符号 / スレショルドディテクタ / カレントミラー / ダイナミック回路 / ソース結合形回路 / 多値算術演算回路 / 多値2線式符号 / 2線式電流モード多値回路 / 電流電圧変換回路 / 出力生成回路 / 電流比較回路 / カレントミラーレス回路 / 電流モード多値回路 / Intelligent Information Processing / Magnitude Comparison / Highly-Parallel Operation / Non-numeric Data Processing / Logic-in-Memory Architecture / Threshold Operation / Floating-Gate MOS Transistor / Multiple-Valued CAM / フローティングゲートMOSトランスジスタ / Intelligent information processing / Magnitude comparison / Fully parallel processing / Non-numeric data processing / Logic-in-memory VLSI architecture / Threshold operation / Floating-gate-MOS pass-transistor network / Multiple-valued content-addressable memory (CAM) / 最適化技術 / 新機能デバイス / バラつき補正技術 / 集積回路 / 回路設計技術 / ロジック回路 / 不揮発性 / CAM / 低電力化技術 / 先端機能デバイス / 高速プロトタイピング / 非同期式制御 / 複号化 / 符号化 / 高速伝送技術 / LDPC符号 / 2線符号 / 非同期通信 / 多値VLSI技術 / 誤り訂正符号 / 高速伝送回路 / 情報機器 / マルチメディア応用 / Rambus / ISSCC / コミュニケーションVLSIプロセッサ / ニューパラダイムコンピユーティング / 高速データ転送技術 / Signed-Digit数系 / 2線相補信号 / 機能分離形CAM / 1トランジスタセル / 量子効果デバイス / デバイスモデルベーストエレクトロニクス / 多値論理関数 / ス-パパスゲート / ソース結合形 / モデルマッチング / 特徴量 / トップダウン / 多値論理回路 / 電流モード / エッジ抽出 … More Except Principal Investigator 高並列演算回路 / Logic-In-Memory VLSI / Dual-Rail Current-Mode Multiple-Valued Integrated Circuit / ロジックインメモリVLSI / 2線式電流モード多値集積回路 / Reed-Muller Expansion / 低消費電力多値集積回路 / 多値集積回路 / 知能集積システム / 高信頼化 / スピントロニクス / 不揮発ロジック / IoT / 集積回路 / シミュレーテッドアニーリング / ストカスティック演算 / クロック埋め込み / 低消費電力化 / シリアル通信 / 通信方式 / 同期/非同期インタフェース / 同期／非同期インタフェース / PLL/DLLレス / 4値レベル信号 / 細粒度パワーゲーティング / 高速シリアル通信 / Nonvolatile Logic-in-Mmemory / Ferro-Electric Device / Fine-Grain Pipelinign / Source-Coupled Logic / ステレオビジョンプロセッサ / パイプライン処理 / 多値VLSIプロセッサ / ソース結合形理論 / パストランジスタ理論 / ドミノ理論 / 電圧・電流ハイブリッドモード多値集積回路 / 不揮発ロジックインメモリ / 強誘電体デバイス / 細粒度パイプライン / フルソースカップルドロジック / Partition Theory / Asynchronous Multiple-Valued VLSI / Highly-Parallel Arithmetic and Logic Circuit / Self Checking Circuit / 電力源制御 / 非同期多値演算回路 / 電流源制御 / 電流モード多値集積回路 / 非同期式多値演算回路 / 分割理論 / Reed-Muller展開 / 非同期式多値VLSI / 算術演算回路 / セルフチェッキング回路 / Interconnection Network / Spacially Parallel Structure / Logic-In-Memory Architecture / Allocation / Scheduling / High-Level Synthesis / Intelligent Integrated Systems for Real-World Applications / 3次元計測VLSIプロセッサ / パイプライン並列構造 / ステレオビジョンVLSIプロセッサ / 衝突チェックVLSIプロセッサ / 並列データ供給 / 演算遅れ時間最小化 / 並列構造VLSIプロセッサ / ロジックインメモリアーキテクチャ / 相互結合回路網 / 空間並列構造 / ロジックインメモリアーキテクチャ構造 / アロケーション / スケジューリング / ハイレベルシンセシス / リアルワールド応用知能集積システム / One-Transistor CAM Cell / Multiple-Valued Memory / Multiple-Valued Threshold Operation / Magnitude Comparison / Multiple-Valued CAM / Highly Safe Vehicle / Floating-Gate MOS Transistor / Danger-Detection Rules / 非数値データ処理 / フローティングゲートMOSトランジスタ / 多値連想メモリ / 1トランジスタセル / 多値記憶 / 多値しきい演算 / 大小比較演算 / 多値CAM / 高安全自動車 / フローティングゲートMOSFET / 危険検出ルール / Low Power Multiple-Valued Integrated Circuit / Multiple-Valued Current-Mode Integrated Circuit / Redundant Coding / Critical-Path Minimization / Linear Digital Circuit / Highly Parallel Arithmetic and Logic Circuit / リ-ドマラ-展開 / 超高並列演算システム / クリティカルパス遅延最小化 / 多値電流モード集積回路 / 多値冗長符号 / リ-ド・マラ-展開 / 線形演算回路 / Multiple-Valued Integrated Devices / Device-Model Based Electronics / Small Interconnection Delay / Small Critical-Delay Path / Ultra Fine Integrated Circuits / Linear Digital System / Highly Parallel Multiple-Valued Arithmetic and Logic Circuits / Intelligent Integrated Systems / 空間的並列構造プロセッサ / 専用VLSIプロセッサ / 多値情報処理 / 多値集積デバイス / デバイスモデルベーストエレクトロニクス / 微小配線遅延 / 微小クリティカルパス遅延 / 超微細集積回路 / 線形ディジタルシステム / 高並列多値演算回路 / 3-D Object Recognition / Clique Finding / Graph Matching / Object Recognition System / Inference VLSI Chip / Floating-Gate MOS-FET / Pattern Matching Cell / 4-Valued CMOS Integrated Circuit / フロ-ティングゲ-トMOS-FET / パタ-ンマッチングセル / 超高速推論ハ-ドウェアエンジン / VLSIアレー / 知的情報処理 / 3次元物体認識 / クリーク抽出 / グラフマッチング / 物体認識システム / 推論チップ / フローティングゲートMOS-FET / パターンマッチングセル / 4値CMOS集積回路 / Multiple-Valued Super Chip / SD Multiplier / Modular Realization / SD Full-Adder / Multiple-Valued Bidirectional Current-Mode / SD Number System / 4進SD数加算器 / 高速算術演算用アレ- / 知能ロボット / セミカスタムVLSI / 設計容易性 / 指定配線数 / 多値モジュ-ルアレ- / 多値双方向電流モ-ド回路 / 多値SD数演算回路 / 知能ロボット用プロセッサ / ス-パ-チップ / 演算遅れ時間最小 / ロボットビジョン用VLSI / ロボット制御用VLSI / 4進SD数全加算器 / 多値双方向電流モ-ド / 多値ス-パ-チップ / 対称R進数 / SD数系 Less

Development of a high-speed and ultra-low-power die-hard logic LSI fundamental technology for IoT applicationsPrincipal Investigator
- Principal Investigator
  
  羽生貴弘
- Project Period (FY)
  2021 – 2024
- Research Category
  
  Grant-in-Aid for Scientific Research (A)
- Review Section
  
  Medium-sized Section 60:Information science, computer engineering, and related fields
- Research Institution
  Tohoku University
確率的デバイスモデルに基づく量子モンテカルロ計算ハードウェアプラットフォーム構築
- Principal Investigator
  
  鬼沢直哉
- Project Period (FY)
  2021 – 2024
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Tohoku University
スピントロニクスベース高性能・省電力・高信頼IoTセンサノードの基盤研究開発
- Principal Investigator
  
  夏井雅典
- Project Period (FY)
  2021 – 2024
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Tohoku University
脳型コンピューティング向けダーク・シリコンロジックLSIの基盤技術開発Principal Investigator
- Principal Investigator
  
  羽生貴弘
- Project Period (FY)
  2016
- Research Category
  
  Grant-in-Aid for Scientific Research (A)
- Research Field
  
  Computer system
- Research Institution
  Tohoku University
Fundamental Technology Development of Dark-Silicon Logic LSI for Brain-Inspired ComputingPrincipal Investigator
- Principal Investigator
  
  Hanyu Takahiro
- Project Period (FY)
  2016 – 2020
- Research Category
  
  Grant-in-Aid for Scientific Research (S)
- Research Field
  
  Computer system
- Research Institution
  Tohoku University
Study on Implementation for Greatly Reducing Power Dissipation of Serial Communication Mechanisms
- Principal Investigator
  
  YONEDA Tomohiro
- Project Period (FY)
  2015 – 2017
- Research Category
  
  Grant-in-Aid for Scientific Research (A)
- Research Field
  
  Communication/Network engineering
- Research Institution
  National Institute of Informatics
Nonvolatile-device-based PVT-variation-resilient VLSI systemPrincipal Investigator
- Principal Investigator
  
  HANYU TAKAHIRO
- Project Period (FY)
  2010 – 2013
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Tohoku University
Implementation of a High-Speed LDPC Decoder LSI Based on a Multiple-Valued Full-Duplex Data-Transfer TechniquePrincipal Investigator
- Principal Investigator
  
  HANYU Takahiro
- Project Period (FY)
  2006 – 2008
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Tohoku University
不揮発性デバイスに基づくクイックオンVLSIシステムの構成Principal Investigator
- Principal Investigator
  
  羽生貴弘
- Project Period (FY)
  2006 – 2007
- Research Category
  
  Grant-in-Aid for Exploratory Research
- Research Field
  
  Computer system/Network
- Research Institution
  Tohoku University
Implementation of a High-Speed Asynchronous Data Transfer VLSI Based on Bidirectional Current-Mode Multiple-Valued Circuit TechniquesPrincipal Investigator
- Principal Investigator
  
  HANYU Takahiro
- Project Period (FY)
  2003 – 2005
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system/Network
- Research Institution
  Tohoku University
多値技術に基づく高速データ転送とそのマルチメディアVLSIプロセッサへの応用Principal Investigator
- Principal Investigator
  
  羽生貴弘
- Project Period (FY)
  2002
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  計算機科学
- Research Institution
  Tohoku University
Implementation of a Transfer-Bottleneck-Free Multiple-Valued Logic-in-Memory VLSI and Its ApplicationPrincipal Investigator
- Principal Investigator
  
  HANYU Takahiro
- Project Period (FY)
  2001 – 2004
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  計算機科学
- Research Institution
  Tohoku University
Interconnection-Bottleneck-Free VLSI System Based on Dual-Rail Multiple-Valued Digital Computing
- Principal Investigator
  
  KAMEYAMA MICHITAKA
- Project Period (FY)
  2000 – 2002
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  計算機科学
- Research Institution
  Tohoku University
Implementation of a High-Performance Multiple-Valued Current-Mode VLSI System with Low-Power and Highly Reliable CapabilitiesPrincipal Investigator
- Principal Investigator
  
  HANYU Takahiro
- Project Period (FY)
  2000 – 2002
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  計算機科学
- Research Institution
  Tohoku University
高速・低電力電流モード多値算術演算VLSI回路の試作Principal Investigator
- Principal Investigator
  
  羽生貴弘
- Project Period (FY)
  1998 – 1999
- Research Category
  
  Grant-in-Aid for Encouragement of Young Scientists (A)
- Research Field
  
  計算機科学
- Research Institution
  Tohoku University
MULTIPLE-VALUED PROCESSOR FOR INTELLIGENT INTEGRATED SYSTEMPrincipal Investigator
- Principal Investigator
  
  HANYU Takahiro
- Project Period (FY)
  1997 – 1998
- Research Category
  
  Grant-in-Aid for international Scientific Research
- Research Field
  
  計算機科学
- Research Institution
  TOHOKU UNIVERSITY
High-Level Synthesis of High-Performance VLSI Processors for Intelligent Integrated System
- Principal Investigator
  
  KAMEYAMA Michitaka
- Project Period (FY)
  1997 – 1999
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  計測・制御工学
- Research Institution
  TOHOKU UNIVERSITY
Development of a Chip Family for Ultra-Highly-Parallel Multiple-Valued Integrated Circuits and Its Applications
- Principal Investigator
  
  KAMEYAMA Michitaka
- Project Period (FY)
  1997 – 1999
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  計算機科学
- Research Institution
  TOHOKU UNIVERSITY
Implementation of a One-Transistor Multiple-Valued Content-Addressalbe Memory and Its ApplicationPrincipal Investigator
- Principal Investigator
  
  HANYU Takahiro
- Project Period (FY)
  1997 – 2000
- Research Category
  
  Grant-in-Aid for Scientific Research (B).
- Research Field
  
  計算機科学
- Research Institution
  Tohoku Univesity
超並列多値連想メモリに関する研究Principal Investigator
- Principal Investigator
  
  羽生貴弘
- Project Period (FY)
  1996
- Research Category
  
  Grant-in-Aid for Encouragement of Young Scientists (A)
- Research Field
  
  計算機科学
- Research Institution
  Tohoku University
Study on Multiple-Valued VLSI Processors for a Highly Safe Intelligent Vehicle
- Principal Investigator
  
  KAMEYAMA Michitaka
- Project Period (FY)
  1995 – 1996
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  計算機科学
- Research Institution
  Tohoku University
次世代デバイスに基づく高性能多値VLSIシステムの構成に関する研究Principal Investigator
- Principal Investigator
  
  羽生貴弘
- Project Period (FY)
  1994
- Research Category
  
  Grant-in-Aid for Encouragement of Young Scientists (A)
- Research Field
  
  計算機科学
- Research Institution
  Tohoku University
Ultra-Highly-Parallel Arithmetic and Logic Circuits and Their Multiple-Valued Integration
- Principal Investigator
  
  KAMEYAMA Michitaka
- Project Period (FY)
  1994 – 1996
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  計算機科学
- Research Institution
  Tohoku University, Graduate School of Information Sciences
ロボットビジョン用特徴抽出VLSIプロセッサシステムの構成に関する研究Principal Investigator
- Principal Investigator
  
  羽生貴弘
- Project Period (FY)
  1993
- Research Category
  
  Grant-in-Aid for Encouragement of Young Scientists (A)
- Research Field
  
  計測・制御工学
- Research Institution
  Tohoku University
Study on Post-Binary ULSI Sstems
- Principal Investigator
  
  KAMEYAMA Michitaka
- Project Period (FY)
  1992 – 1993
- Research Category
  
  Grant-in-Aid for international Scientific Research
- Research Institution
  Tohoku University, Graduate School of Information Sciences
IMPLEMENTATION OF ULTRA-HIGH-SPEED INFERENCE HARDWARE ENGINE BASED ON 4-VALUED CMOS INTEGRATED CIRCUITS AND ITS APPLICATION
- Principal Investigator
  
  HIGUCHI Tatsuo
- Project Period (FY)
  1991 – 1992
- Research Category
  
  Grant-in-Aid for Developmental Scientific Research (B)
- Research Field
  
  計測・制御工学
- Research Institution
  TOHOKU UNIVERSITY
BASIC STUDY ON HIGH-PERFORMANCE MULTIPLE-VALUED SUPER CHIP FOR INTELLIGENT ROBOTS
- Principal Investigator
  
  HIGUCHI Tatsuo
- Project Period (FY)
  1989 – 1991
- Research Category
  
  Grant-in-Aid for General Scientific Research (B)
- Research Field
  
  計測・制御工学
- Research Institution
  TOHOKU UNIVERSITY

[Book] Applications of Ising Models Based on Stochastic Computing, Chapter of Stochastic Computing: Design and Applications of Emerging Computer Systems2024
- Author(s)
  D. Shin, N. Onizawa, W. J. Gross and T. Hanyu
- Total Pages
  16
- Publisher
  Springer
- ISBN
  9783030037291
- Data Source
  KAKENHI-PROJECT-23K21650
[Book] Beyond MRAM: Nonvolatile Logic-in-Memory VLSI, Chapter 7 in Book: Introduction to Magnetic Random-Access Memory2016
- Author(s)
  Takahiro Hanyu, Tetsuo Endoh, Shoji Ikeda, Tadahiko Sugibayashi, Naoki Kasai, Daisuke Suzuki, Masanori Natsui, Hiroki Koike, and Hideo Ohno
- Total Pages
  264
- Publisher
  Wiley-IEEE Press
- ISBN
  9781119009740
- Data Source
  KAKENHI-PROJECT-16H06300
[Journal Article] Enhanced convergence in p-bit based simulated annealing with partial deactivation for large-scale combinatorial optimization problems2024
- Author(s)
  Onizawa Naoya、Hanyu Takahiro
- Journal Title
  
  Scientific Reports
  
  Volume: 14 Issue: 1 Pages: 1339-1339
- DOI
  10.1038/s41598-024-51639-x
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-23K21650
[Journal Article] Design of an energy-efficient nonvolatile lookup table circuit using active-load-localized circuitry with self-terminated writing/reading2023
- Author(s)
  Suzuki Daisuke、Hanyu Takahiro
- Journal Title
  
  Japanese Journal of Applied Physics
  
  Volume: 62 Issue: SC Pages: SC1099-SC1099
- DOI
  10.35848/1347-4065/acbd5a
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21H04868
[Journal Article] Design of a Nonvolatile-Register-Embedded RISC-V CPU with Software-Controlled Data-Retention and Hardware-Acceleration Functions2023
- Author(s)
  M. Natsui, K. Sakamoto, and T. Hanyu
- Journal Title
  
  Memories - Materials, Devices, Circuits and Systems
  
  Volume: 4 Pages: 100035-100035
- DOI
  10.1016/j.memori.2023.100035
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-17KK0001, KAKENHI-PROJECT-23K21651, KAKENHI-PROJECT-21H04868
[Journal Article] Local Energy Distribution Based Hyperparameter Determination for Stochastic Simulated Annealing2023
- Author(s)
  Onizawa Naoya、Kuroki Kyo、Shin Duckgyu、Hanyu Takahiro
- Journal Title
  
  IEEE Open Journal of Signal Processing
  
  Volume: 4 Pages: 452-461
- DOI
  10.1109/ojsp.2023.3329756
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-23K21650
[Journal Article] Self-Adaptive Gate Control for Efficient Escape From Local Minimum Energy on Invertible Logic2023
- Author(s)
  Onizawa Naoya、Yano Koji、Shin Seiichi、Fujita Hiroyuki、Hanyu Takahiro
- Journal Title
  
  IEEE Access
  
  Volume: 11 Pages: 44923-44931
- DOI
  10.1109/access.2023.3272867
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-23K21650
[Journal Article] Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing2023
- Author(s)
  Shin Duckgyu、Onizawa Naoya、Gross Warren J.、Hanyu Takahiro
- Journal Title
  
  IEEE Journal on Emerging and Selected Topics in Circuits and Systems
  
  Volume: 13 Issue: 1 Pages: 108-118
- DOI
  10.1109/jetcas.2023.3243260
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21650
[Journal Article] Fast-Converging Simulated Annealing for Ising Models Based on Integral Stochastic Computing2022
- Author(s)
  Onizawa Naoya、Katsuki Kota、Shin Duckgyu、Gross Warren J.、Hanyu Takahiro
- Journal Title
  
  IEEE Transactions on Neural Networks and Learning Systems
  
  Volume: - Issue: 12 Pages: 1-7
- DOI
  10.1109/tnnls.2022.3159713
- Peer Reviewed / Open Access / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21650
[Journal Article] Implementation of CMOS Invertible Logic on Zynq-SoC Platform: A Case Study of Training BNN2022
- Author(s)
  D. Shin, N. Onizawa, and T. Hanyu
- Journal Title
  
  Journal of Applied Logics
  
  Volume: 9-3 Pages: 585-606
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-23K21650
[Journal Article] Dynamic activation of power-gating-switch configuration for highly reliable nonvolatile large-scale integrated circuits2022
- Author(s)
  F. Zhong, M. Natsui, and T. Hanyu
- Journal Title
  
  Japanese Journal of Applied Physics
  
  Volume: 61
- DOI
  10.35848/1347-4065/ac461a
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-17KK0001, KAKENHI-PROJECT-23K21651
[Journal Article] Design of an active-load-localized single-ended nonvolatile lookup-table circuit for energy-efficient binary-convolutional-neural-network accelerator2022
- Author(s)
  SUZUKI Daisuke, OKA Takahiro、HANYU Takahiro
- Journal Title
  
  Japanese Journal of Applied Physics
  
  Volume: 61 Issue: SC Pages: SC1083-SC1083
- DOI
  10.35848/1347-4065/ac51bf
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20K11725, KAKENHI-PROJECT-21H04868
[Journal Article] CMOS Invertible Logic: Bidirectional operation based on the probabilistic device model and stochastic computing2022
- Author(s)
  Onizawa Naoya、Hanyu Takahiro
- Journal Title
  
  IEEE Nanotechnology Magazine
  
  Volume: 16 Issue: 1 Pages: 33-46
- DOI
  10.1109/mnano.2021.3126094
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23K21650
[Journal Article] Design of a highly reliable nonvolatile flip-flop incorporating a common-mode write error detection capability2021
- Author(s)
  M. Natsui, G. Yamagishi, and T. Hanyu
- Journal Title
  
  Japanese Journal of Applied Physics
  
  Volume: 60 Issue: SB Pages: SBBB02-SBBB02
- DOI
  10.35848/1347-4065/abdcb0
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17KK0001, KAKENHI-PROJECT-23K21651
[Journal Article] Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN2021
- Author(s)
  Arakawa Ren、Onizawa Naoya、Diguet Jean-Philippe、Hanyu Takahiro
- Journal Title
  
  IEEE Transactions on Circuits and Systems I: Regular Papers
  
  Volume: 68 Issue: 1 Pages: 67-76
- DOI
  10.1109/tcsi.2020.3030104
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H06300
[Journal Article] High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians2021
- Author(s)
  Onizawa Naoya、Hanyu Takahiro
- Journal Title
  
  2021 IEEE International Symposium on Circuits and Systems (ISCAS)
  
  Volume: - Pages: 1-5
- DOI
  10.1109/iscas51556.2021.9401278
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23K21650
[Journal Article] New-Paradigm Logic-LSI Design Technology Based on Nonvolatile Storage Functionality and Its Future Prospects2021
- Author(s)
  夏井雅典、羽生貴弘
- Volume
  J104-C
- Issue
  6
- Pages
  185-192
- DOI
  10.14923/transelej.2020JCI0011
- ISSN
  1881-0217
- Year and Date
  2021-06-01
- Language
  Japanese
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-16H06300, KAKENHI-PROJECT-21H04868
[Journal Article] 不揮発記憶機能が拓く新概念ロジックLSI設計技術とその将来展望2021
- Author(s)
  夏井雅典, 羽生貴弘
- Journal Title
  
  電子情報通信学会論文誌C
  
  Volume: Vol.J104-C, No.6 Pages: 185-192
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-23K21651
[Journal Article] Design of an MTJ-based Nonvolatile Multi-context Ternary Content-Addressable Memory2020
- Author(s)
  N. Onizawa, R. Arakawa, and T. Hanyu
- Journal Title
  
  Journal of Applied Logics
  
  Volume: 7 Pages: 89-105
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-16H06300
[Journal Article] Prospects of Edge AI Hardware Using Nonvolatile Logic2020
- Author(s)
  HANYU Takahiro
- Journal Title
  
  IEICE ESS Fundamentals Review
  
  Volume: 13 Issue: 4 Pages: 269-276
- DOI
  10.1587/essfr.13.4_269
- NAID
  130007825861
- ISSN
  1882-0875
- Year and Date
  2020-04-01
- Language
  Japanese
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-16H06300
[Journal Article] Networked Power-Gated MRAMs for Memory-Based Computing2018
- Author(s)
  J.-P. Diguet, N. Onizawa, M. Rizk, M. J. Sepulveda, A. Baghdadi, and T. Hanyu
- Journal Title
  
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  
  Volume: 26 Issue: 12 Pages: 2696-2708
- DOI
  10.1109/tvlsi.2018.2856458
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H06300
[Journal Article] MTJ-Based Asynchronous Circuits for Re-Initialization Free Computing against Power Failures2018
- Author(s)
  N. Onizawa, M. Imai, T. Yoneda, and T. Hanyu
- Journal Title
  
  Microelectronics Journal
  
  Volume: 82 Pages: 46-61
- DOI
  10.1016/j.mejo.2018.10.012
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-16H06300
[Journal Article] Soft/Write-Error Resilient CMOS/MTJ Nonvolatile Flip-Flop Based on Majority-Decision Shared Writing2017
- Author(s)
  Naoya Onizawa and Takahiro Hanyu
- Journal Title
  
  Japanese Journal of Applied Physics
  
  Volume: 56, 4S
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H06300
[Journal Article] Design of a Variation-Resilient Single-Ended Nonvolatile 6-Input Lookup Table Circuit with a Redundant-MTJ-Based Active Load for Smart IoT Applications2017
- Author(s)
  D. Suzuki, M. Natsui, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu
- Journal Title
  
  Institute of Engineering Technology (IET), Electronics Letters
  
  Volume: 53, 7 Pages: 456-458
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H06300
[Journal Article] Design of a Low-Power Nonvolatile Flip-Flop Using 3-Terminal Magnetic-Tunnel-Junction-Based Self-Terminated Mechanism2017
- Author(s)
  Daisuke Suzuki and Takahiro Hanyu
- Journal Title
  
  Japanese Journal of Applied Physics
  
  Volume: 56, 4S
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H06300
[Journal Article] Fabrication of an MTJ-Based Nonvolatile Logic-in-Memory LSI with Content-Aware Write Error Masking Scheme Achieving 92% Storage Capacity and 79% Power Reduction2017
- Author(s)
  Masanori Natsui, Akira Tamakoshi, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu
- Journal Title
  
  Japanese Journal of Applied Physics
  
  Volume: 56, 4S
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H06300
[Journal Article] Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing2016
- Author(s)
  T. Hanyu, T. Endoh, D. Suzuki, H. Koike, Y. Ma, N. Onizawa, M. Natsui, S. Ikeda, and H. Ohno
- Journal Title
  
  Proc. of the IEEE
  
  Volume: 104 Issue: 10 Pages: 1843-1863
- DOI
  10.1109/jproc.2016.2574939
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26700003, KAKENHI-PROJECT-16K12494, KAKENHI-PROJECT-16H06300
[Journal Article] Analog-to-Stochastic Converter Using Magnetic Tunnel Junction Devices for Vision Chips2016
- Author(s)
  N. Onizawa, D. Katagiri, W. J. Gross, and T. Hanyu
- Journal Title
  
  IEEE Trans. on Nanotechnology
  
  Volume: 15 Issue: 5 Pages: 705-714
- DOI
  10.1109/tnano.2015.2511151
- Peer Reviewed / Acknowledgement Compliant / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26700003, KAKENHI-PROJECT-16K12494, KAKENHI-PROJECT-16H06300
[Journal Article] Design and Evaluation of a Differential Switching Gate for Low-Voltage Applications2013
- Author(s)
  M. Natsui, K. Kashiuchi, and T. Hanyu
- Journal Title
  
  43rd IEEE International Symposium on Multiple-Valued Logic (ISMVL2013)
  
  Pages: 147-151
- DOI
  10.1109/ismvl.2013.23
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22360137
[Journal Article] MTJ/MOS-Hybrid Logic-Circuit Design Flow for Nonvolatile Logic-in-Memory LSI2013
- Author(s)
  M. Natsui, N. Sakimura, T. Sugibayashi, and T. Hanyu
- Journal Title
  
  2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)
  
  Pages: 105-108
- DOI
  10.1109/iscas.2013.6571793
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22360137
[Journal Article] Design of Process-Variation-Resilient Analog Basic Components Using Magnetic-Tunnel-Junction Devices2013
- Author(s)
  M. Natsui and T. Hanyu
- Journal Title
  
  Journal of Multiple-Valued Logic and Soft Computing
  
  Volume: Vol.21, No.5-6 Pages: 597-608
- URL
  http://www.oldcitypublishing.com/pdf/3498
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22360137
[Journal Article] Process-Variation-Resilient OTA Using MTJ-Based Multi-Level Resistance Control2012
- Author(s)
  M. Natsui, T. Nagashima, and T. Hanyu
- Journal Title
  
  42nd IEEE International Symposium on Multiple-Valued Logic (ISMVL2012)
  
  Pages: 214-219
- DOI
  10.1109/ismvl.2012.52
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22360137
[Journal Article] Process-Variation-Resilient OTA Using MTJ-Based Multi-Level Resistance Control2012
- Author(s)
  M.Natsui, T.Nagashima, T.Hanyu
- Journal Title
  
  Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic
  
  Volume: (掲載確定)
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22360137
[Journal Article] Variation-Resilient Current-Mode Logic Circuit Design Using MTJ Devices2012
- Author(s)
  Y.Kim, M.Natsui, T.Hanyu
- Journal Title
  
  Proceedings of 2012 IEEE International Symposium on Circuits & Systems
  
  Volume: (掲載確定)
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22360137
[Journal Article] Scalable Serial-Configuration Scheme for MTJ/MOS-Hybrid Variation-Resilient VLSI System2012
- Author(s)
  M. Natsui and T. Hanyu
- Journal Title
  
  10th IEEE International NEWCAS Conference (NEWCAS2012)
  
  Pages: 97-100
- DOI
  10.1109/newcas.2012.6328965
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22360137
[Journal Article] Low-Energy Pipelined Multiple-Valued Current-Mode Circuit Based on Current-Level Control Technique2012
- Author(s)
  M. Natsui, T. Arimitsu and T. Hanyu
- Journal Title
  
  Journal of Multiple-Valued Logic and Soft Computing
  
  Volume: Vol.19, No.1-3 Pages: 219-231
- URL
  http://www.oldcitypublishing.com/pdf/2910
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22360137
[Journal Article] Variation-Resilient Current-Mode Logic Circuit Design Using MTJ Devices2012
- Author(s)
  Y. Kim, M. Natsui and T. Hanyu
- Journal Title
  
  2012 IEEE International Symposium on Circuits & Systems (ISCAS2012)
  
  Pages: 2705-2708
- DOI
  10.1109/iscas.2012.6271866
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22360137
[Journal Article] Low-Energy Pipelined Multiple-Valued Current-Mode Circuit Based on Current-Level Control Technique2012
- Author(s)
  M.Natsui, T.Arimitsu, T.Hanyu
- Journal Title
  
  Journal of Multiple-Valued Logic and Soft Computing
  
  Volume: (未定)(掲載確定)
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22360137
[Journal Article] MTJ-Based Optimal Vth-Tuning Technique for a Process-Variation-Aware VLSI processor2011
- Author(s)
  M.Natsui, Y.Kim, T.Hanyu
- Journal Title
  
  Proceedings of the 56th Magnetism and Magnetic Materials Conference
  
  Pages: 480-481
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22360137
[Journal Article] MTJ-Based Optimal Vth-Tuning Technique for a Process-Variation-Aware VLSI processor2011
- Author(s)
  M. Natsui, Y. Kim and T. Hanyu
- Journal Title
  
  The 56th Magnetism and Magnetic Materials Conference (MMM2011)
  
  Pages: 480-481
- URL
  http://www.magnetism.org/
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22360137
[Journal Article] High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving2009
- Author(s)
  N. Onizawa, T. Hanyu and V. C. Gaudet
- Journal Title
  
  IEICE Trans. Electron (掲載決定)
- NAID
  10026822478
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] Design of High-Throughput Fully-Parallel LDPC Decoders Based on Wire Partitioning2009
- Author(s)
  N. Onizawa, T. Hanyu and V.C. Gaudet
- Journal Title
  
  IEEE Trans. on VLSI Systems (掲載決定)
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] Design of High-Throughput Fully-Parallel LDPC Decoders Based on Wire Partitioning2009
- Author(s)
  Naoya Onizawa, Takahiro Hanyu, and Vincent C. Gaudet
- Journal Title
  
  IEEE Trans. on VLSI Systems (採録決定)
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving Date of Evaluation2009
- Author(s)
  Naoya Onizawa, Takahiro Hanyu, and Vincent C. Gaudet
- Journal Title
  
  IEICE Trans. Electron (採録決定)
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] Power-Aware Asynchronous Peer-to-Peer Duplex Communication System Based on Multiple-Valued One-Phase Signaling2008
- Author(s)
  K. Mizusawa, N. Onizawa and T. Hanyu
- Journal Title
  
  IEICE Trans. Electron Vol.E91-C, No.4
  
  Pages: 581-588
- NAID
  10026817575
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation2008
- Author(s)
  M. Miura and T. Hanyu
- Journal Title
  
  IEICE Trans. Electron Vol.E91-C, No.4
  
  Pages: 589-594
- NAID
  10026817589
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] 多値電流モード非同期データ転送方式に基づくLDPCデコーダLSIの実現2007
- Author(s)
  鬼沢直哉, 羽生貴弘
- Journal Title
  
  電子情報通信学会総合大会講演論文集
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] TMRロジックに基づく低消費電力FPGAの構成と評価2007
- Author(s)
  渡邊康広, 羽生貴弘
- Journal Title
  
  電子情報通信学会「多値論理とその応用」第二種研究会技術報告 MVL-07・1
  
  Pages: 1-7
- Data Source
  KAKENHI-PROJECT-18650009
[Journal Article] Design of a Fluid Analysis Simulator Based on Lattice Gas Cellular Automaton2007
- Author(s)
  D.Suzuki, T.Hanyu
- Journal Title
  
  Proc. 4th International Symposium on System Construction of Global-Network-Oriented Information Electronics 4
  
  Pages: 330-331
- Data Source
  KAKENHI-PROJECT-18650009
[Journal Article] 電流モード多値回路の信頼性評価2007
- Author(s)
  高橋知宏, 羽生貴弘
- Journal Title
  
  電子情報通信学会総合大会講演論文集
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] トンネル磁気抵抗デバイスによる論理集積回路-不揮発性が拓く次世代ロジックLSIパラダイム-2007
- Author(s)
  羽生貴弘
- Journal Title
  
  応用物理第76巻,第12号
  
  Pages: 1388-1393
- NAID
  10020007373
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18650009
[Journal Article] Implementation of a High-Throughput LDPC Decoder Chip Using an Asynchronous Interleaving Scheme2007
- Author(s)
  N.Onizawa, T.Hanyu
- Journal Title
  
  Proc. 4th International Symposium on System Construction of Global-Network-Oriented Information Electronics 4
  
  Pages: 398-399
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] Design and Evaluation of a 54x54-bit Multiplier Based on Differential-Pair Circuitry2007
- Author(s)
  Akira Mochizuki, Hirokatsu Shirahama and Takahiro Hanyu
- Journal Title
  
  IEICE Trans. on Electronics E90-C・4
  
  Pages: 683-691
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] Nonvolatile Static Latch Based on Ferroelectric Defferential Logic2007
- Author(s)
  S.Matsunaga, T.Hanyu
- Journal Title
  
  Proc. 4th International Symposium on System Construction of Global-Network-Oriented Information Electronics 4
  
  Pages: 334-335
- Data Source
  KAKENHI-PROJECT-18650009
[Journal Article] A Simplex/Duplex-Compatible System for Asynchronous Peer-to-Peer Communication Using One-phase Signaling2007
- Author(s)
  T.Takahashi, T.Hanyu
- Journal Title
  
  Proc. 4th International Symposium on System Construction of Global-Network-Oriented Information Electronics 4
  
  Pages: 338-339
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] Novel Circuit Techniques for High-Speed Intra-Chip Communication2007
- Author(s)
  T.Hanyu, T.Takahashi, S.Matsunaga
- Journal Title
  
  Proc. 4th International Symposium on System Construction of Global-Network-Oriented Information Electronics 4
  
  Pages: 134-139
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] Design and Evaluation of a 54x54-bit Multiplier Based on Differential-Pair Circuitry2007
- Author(s)
  A. Mochizuki, H. Shirahama and T. Hanyu
- Journal Title
  
  IEICE Trans. on Electronics Vol.E90-C, No.4
  
  Pages: 683-691
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic2007
- Author(s)
  S.Matsunaga, T.Hanyu, H.Kimura, T.Nakamura, H.Takasu
- Journal Title
  
  Proc. Asia and South Pacific Design Automation Conf.
  
  Pages: 116-117
- Data Source
  KAKENHI-PROJECT-18650009
[Journal Article] Magnetic Tunnel Junctions for Spintronic Memories and Beyond2007
- Author(s)
  Shoji Ikeda, Jun Hayakawa, Young Min Lee, Fumihiro Matsukura, Yuzo Ohno, Takahiro Hanyu, and Hideo Ohno
- Journal Title
  
  IEEE Transactions on Electron Devices Vol.54, No.5
  
  Pages: 991-1002
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18650009
[Journal Article] 流体解析用格子ガスセルラアレーVLSIのFPGA実現2007
- Author(s)
  鈴木大輔, 羽生貴弘
- Journal Title
  
  電子情報通信学会総合大会講演論文集
- Data Source
  KAKENHI-PROJECT-18650009
[Journal Article] Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits2006
- Author(s)
  A.Mochizuki, T.Kitamura, H.Shirahama, T.Hanyu
- Journal Title
  
  Proc. 36th IEEE International Symposium on Multiple-Valued Logic 36(CD-ROM版のため頁番号なし)
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic2006
- Author(s)
  A.Mochizuki, H.Shirahama, T.Hanyu
- Journal Title
  
  IEICE Trans. on Electronics E89-C・11
  
  Pages: 1575-1580
- NAID
  110007538696
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic2006
- Author(s)
  A. Mochizuki, H. Shirahama and T. Hanyu
- Journal Title
  
  IEICE Trans. on Electronics Vol.E89-C, No.11
  
  Pages: 1575-1580
- NAID
  110007538696
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-Valued Current-Signal Multiplexing2006
- Author(s)
  T.Takahashi, T.Hanyu
- Journal Title
  
  IEICE Trans. on Electronics E89-C? 11
  
  Pages: 1598-1604
- NAID
  110007538697
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] TMRロジックに基づく低消費電力TCAMの構成2006
- Author(s)
  木村圭, 渡邊康広, 羽生貴弘
- Journal Title
  
  平成18年度電気関係学会東北支部連合大会講演論文集 1F7
  
  Pages: 206-206
- NAID
  130005444064
- Data Source
  KAKENHI-PROJECT-18650009
[Journal Article] 多値2 線符号化に基づく高性能非同期データ転送VLSI2006
- Author(s)
  高橋知宏, 水澤一泰, 羽生貴弘
- Journal Title
  
  電子情報通信学会「集積回路研究会」技術報告 106・315
  
  Pages: 37-42
- NAID
  10018637790
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] 2線差動論理に基づくノイズフリー多値集積回路2006
- Author(s)
  三浦成友, 望月明, 羽生貴弘
- Journal Title
  
  平成18年度電気関係学会東北支部連合大会講演論文集
  
  Pages: 341-341
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] 差動ロジックに基づく高性能VLSIの展望2006
- Author(s)
  望月明, 羽生貴弘
- Journal Title
  
  多値論理研究ノート 29
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic2006
- Author(s)
  N. Onizawa and T. Hanyu
- Journal Title
  
  IEICE Trans. on Electronics Vol.E89-C, No.11
  
  Pages: 1591-1597
- NAID
  110007538694
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic2006
- Author(s)
  N.Onizawa, T.Hanyu
- Journal Title
  
  IEICE Trans. on Electronics E89-C? 11
  
  Pages: 1591-1597
- NAID
  110007538694
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] 隣接データの類似性に着目した高速LDPC復号化とその評価2006
- Author(s)
  池田智和, 鬼沢直哉, 羽生貴弘
- Journal Title
  
  平成18年度電気関係学会東北支部連合大会講演論文集
  
  Pages: 70-70
- NAID
  130005444329
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] 多値2線符号化に基づく双方向非同期データ転送LSI の高性能化2006
- Author(s)
  水澤一泰, 高橋知宏, 羽生貴弘
- Journal Title
  
  平成18年度電気関係学会東北支部連合大会講演論文集
  
  Pages: 342-342
- NAID
  130005444266
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-Valued Current-Signal Multiplexing2006
- Author(s)
  T. Takahashi, T. Hanyu
- Journal Title
  
  IEICE Trans. on Electronics Vol. E89-C, No.11
  
  Pages: 1598-1604
- NAID
  110007538697
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] Ferroelectric-Based Logic Circuit and Its Application to Content-Addressable Memory2006
- Author(s)
  H.Kimura, Y.Fujimori, T.Nakamura, H.Takasu, T.Hanyu
- Journal Title
  
  Proceeding of IEEE The 2006 International Meeting for Future Electron Devices
  
  Pages: 41-42
- Data Source
  KAKENHI-PROJECT-18650009
[Journal Article] Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic2006
- Author(s)
  A.Mochizuki, T.Hanyu
- Journal Title
  
  Proc. 36th IEEE International Symposium on Multiple-Valued Logic 36(CD-ROM版のため頁番号なし)
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] Design of a Fluid Analysis Simulator Based on Lattice Gas Cellular Automaton2006
- Author(s)
  D.Suzuki, T.Hanyu
- Journal Title
  
  Proc. 3rd Workshop of Yeungnum Univ. and Tohoku Univ.
  
  Pages: 132-134
- Data Source
  KAKENHI-PROJECT-18650009
[Journal Article] TMR-Based Differential Logic for Vt-Variation Compansation2006
- Author(s)
  A.Hirosaki, M.Miura, A.Mochizuki, T.Hanyu
- Journal Title
  
  Proc. 3rd Workshop of Yeungnum Univ. and Tohoku Univ.
  
  Pages: 51-52
- Data Source
  KAKENHI-PROJECT-18650009
[Journal Article] Low-power Latch Based on Dynamic Differential Logic2006
- Author(s)
  H.Shirahama, A.Mochizuki, T.Hanyu
- Journal Title
  
  Proc. 3rd Workshop of Yeungnum Univ. and Tohoku Univ 3
  
  Pages: 138-140
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] Automatic Place and Route Scheme in Multiple-Valued Current-Mode Circuit Design2006
- Author(s)
  T.Nagai, T.Takahashi, N.Onizawa, T.Hanyu
- Journal Title
  
  Proc. 3rd Workshop of Yeungnum Univ. and Tohoku Univ. 3
  
  Pages: 57-58
- Data Source
  KAKENHI-PROJECT-18300012
[Journal Article] TMRロジックとその応用2006
- Author(s)
  羽生貴弘, 望月明, 渡邊康広
- Journal Title
  
  応用電子物性分科会誌 12・4
  
  Pages: 154-159
- NAID
  10024270241
- Data Source
  KAKENHI-PROJECT-18650009
[Journal Article] Non-Volatile Logic-in-Memory Circuit and Its Application2005
- Author(s)
  Takahiro Hanyu
- Journal Title
  
  Proc.2nd International Symposium on System Construction of Global-Network-Oriented Information Electronics 2
  
  Pages: 99-102
- Data Source
  KAKENHI-PROJECT-13558026
[Journal Article] Multiple-Valued Dynamic Source-Coupled Logic2003
- Author(s)
  T.Hanyu
- Journal Title
  
  IEEE Int.Symposium on Multiple-Valued Logic 33
  
  Pages: 207-212
- NAID
  120001182151
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15500029
[Journal Article] Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current-Mode Logic2003
- Author(s)
  T.Hanyu
- Journal Title
  
  IEEE Int.Symposium on Multiple-Valued Logic 33
  
  Pages: 99-104
- NAID
  120001182150
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15500029
[Journal Article] Multiple-Valued Dynamic Source-Coupled Logic2003
- Author(s)
  T.Hanyu
- Journal Title
  
  IEEE International Symposium on Multiple-Valued Logic 33
  
  Pages: 207-212
- NAID
  120001182151
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-15500029
[Journal Article] Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current-Mode Logic2003
- Author(s)
  T.Hanyu
- Journal Title
  
  IEEE International Symposium on Multiple-Valued Logic 33
  
  Pages: 99-104
- NAID
  120001182150
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-15500029
[Journal Article] Ferroelectric-Based Functional Pass-Gate for Fine-Grain Pipelined VLSI Computation2002
- Author(s)
  T.Hanyu
- Journal Title
  
  Digest of Technical Papers, IEEE International Solid-State Circuits Conference(ISSCC)
  
  Pages: 208-209
- NAID
  120002338721
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-13558026
[Journal Article] Ferroelectric-Based Functional Pass-Gate for Fine-Grain Pipelined VLSI Computation2002
- Author(s)
  T.Hanyu
- Journal Title
  
  Digest of Technical Papers, IEEE International Solid-State Circuits Conference (ISSCC) 45
  
  Pages: 208-209
- NAID
  120002338721
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-13558026
[Journal Article] Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits2001
- Author(s)
  T.Hanyu
- Journal Title
  
  IEEE 31st International Symposium on Multiple-Valued Logic 31
  
  Pages: 167-172
- NAID
  120002338719
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-13558026
[Journal Article] Challenge of a Multiple-Valued Technology in Recent Deep-Submicron VLSI2001
- Author(s)
  T.Hanyu
- Journal Title
  
  IEEE 31st International Symposium on Multiple-Valued Logic 31
  
  Pages: 241-244
- NAID
  120002338720
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-13558026
[Journal Article] Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits2001
- Author(s)
  T.Hanyu
- Journal Title
  
  IEEE 31st International Symposium on Multiple-Valued Logic
  
  Pages: 167-172
- NAID
  120002338719
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-13558026
[Journal Article] Challenge of a Multiple-Valued Technology in Recent Deep-Submicron VLSI2001
- Author(s)
  T.Hanyu
- Journal Title
  
  IEEE 31st International Symposium on Multiple-Valued Logic
  
  Pages: 241-244
- NAID
  120002338720
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-13558026
[Patent] 最適化装置、最適化方法及ひプログラム2022
- Inventor(s)
  羽生貴弘, 鬼沢直哉，佐々木　遼真
- Industrial Property Rights Holder
  羽生貴弘, 鬼沢直哉，佐々木　遼真
- Industrial Property Rights Type
  特許
- Industrial Property Number
  2022-129728
- Filing Date
  2022
- Data Source
  KAKENHI-PROJECT-23K21650
[Presentation] Stochastic Implementation of Simulated Quantum Annealing on PYNQ2023
- Author(s)
  T. Kubuta, D. Shin, N. Onizawa, and T. Hanyu
- Organizer
  International Conferernce on Field Programmable Technology (ICFPT)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21650
[Presentation] Write-Energy Reduction of MTJ-Based Quantized Neural-Network Hardware2023
- Author(s)
  K. Asano, M. Natsui, and T. Hanyu
- Organizer
  53th IEEE International Symposium on Multiple-Valued Logic (ISMVL2023)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21651
[Presentation] Improving Stochastic Quantum-like Annealing Based on Rerandomization2023
- Author(s)
  R. Sasaki, D. Shin, N. Onizawa, and T. Hanyu
- Organizer
  30th IEEE International Conference on Electrocncis, Circuits & Systems (ICECS)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21650
[Presentation] High-Performance/Low-Area Power-Gating Switch Linear Array for Energy-Efficient LSIs with an Optimum Switch-Timing Control2023
- Author(s)
  F. Zhong, M. Natsui, and T. Hanyu
- Organizer
  2023 IEEE International Symposium on Circuits and Systems(ISCAS2023)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21651
[Presentation] Challenge of a Low-Power FPGA-Based CNN Accelerator Based on Nonvolatile Logic-in-Memory Circuitry2023
- Author(s)
  D. Suzuki, M. Natsui, A. Tamakoshi, Y. Takako, and T. Hanyu
- Organizer
  2023 International Symposium on Nonlinear Theory and Its Applications (NOLTA2023)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21651
[Presentation] Design of an Error-Tolerant Nonvolatile Register for Energy-Aware Intermittent Computing2023
- Author(s)
  K. Sakai, M. Natsui, and T. Hanyu
- Organizer
  The 66th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2023)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21651
[Presentation] Challenge of Energy-Efficient Edge-AI Accelerator Architecture Using Nonvolatile Logic2023
- Author(s)
  M. Natsui, Y. Takako, A. Tamakoshi, and T. Hanyu
- Organizer
  2023 International Symposium on Nonlinear Theory and Its Applications (NOLTA2023)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21651
[Presentation] 高位合成を用いた不揮発AIアクセラレータの高効率設計に関する基礎的研究2023
- Author(s)
  渡邉颯音，夏井雅典，羽生貴弘
- Organizer
  2023年度電気関係学会東北支部連合大会
- Data Source
  KAKENHI-PROJECT-23K21651
[Presentation] Error-Sensitivity-Aware Write-Energy Optimization for an MTJ-Based Binarized Neural Network2023
- Author(s)
  K. Asano, M. Natsui, and T. Hanyu
- Organizer
  30th IEEE International Conference on Electronics Circuits and Systems (ICECS2023)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21651
[Presentation] Impact of Spintronics-Based Nonvolatile Hardware for AI Applications2023
- Author(s)
  T. Hanyu, N. Onizawa, D. Suzuki, and M. Natsui
- Organizer
  2023 International Conference on Solid State Devices and Materials (SSDM2023)
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21651
[Presentation] ビットエラー耐性を活用した省エネルギーニューラルネットワークの構成に関する基礎的研究2022
- Author(s)
  浅野健，夏井雅典，羽生貴弘
- Organizer
  2022年度電気関係学会東北支部連合大会
- Data Source
  KAKENHI-PROJECT-23K21651
[Presentation] MTJベース量子化ニューラルネットワークハードウェアの書込みエネルギー削減手法に関する研究2022
- Author(s)
  浅野健，夏井雅典，羽生貴弘
- Organizer
  ICD学生・若手研究会
- Data Source
  KAKENHI-PROJECT-23K21651
[Presentation] Prospects of Energy-Efficient Edge-AI Accelerator Architecture Using Nonvolatile Logic2022
- Author(s)
  M. Natsui, D. Suzuki, Y. Takako, A. Tamakoshi, and T. Hanyu
- Organizer
  2022 International Symposium on Nonlinear Theory and Its Applications (NOLTA 2022)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21H04868
[Presentation] 書込みエラー特性に基づくMTJベース不揮発レジタの制御部最適化に関する一検討2022
- Author(s)
  酒井楓，夏井楓，夏井雅典，羽生貴弘
- Organizer
  2022年度ICD/CAS学生・若手研究会
- Data Source
  KAKENHI-PROJECT-21H04868
[Presentation] 書込みエラー検出機能を有する高信頼不揮発レジスタの構成2022
- Author(s)
  酒井楓，夏井雅典，羽生貴弘
- Organizer
  2022年度電気関係学会東北支部連合講演会
- Data Source
  KAKENHI-PROJECT-21H04868
[Presentation] 大規模 SC-SA 法の高速求解向け FPGA 実装と評価2022
- Author(s)
  口分田大芽，シントッキュ，鬼沢直哉，羽生貴弘
- Organizer
  2022 年度電気関係学会東北支部連合大会
- Data Source
  KAKENHI-PROJECT-23K21650
[Presentation] Prospects of MTJ-Based Nonvolatile Logic-in-Memory Circuits and Their Applications to AI Hardware2022
- Author(s)
  Takahiro Hanyu
- Organizer
  The 3rd International Symposium on AI and Electronics
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H06300
[Presentation] Energy-Efficient Nonvolatile RISC-V CPU with a Custom Instruction-Controlled Accelerator2022
- Author(s)
  Keisuke Sakamoto，Masanori Natsui, and Takahiro Hanyu
- Organizer
  65th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2022)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21H04868
[Presentation] 不揮発LSI向け可変パワーゲーティングスイッチ構造とその動的制御に関する研究2022
- Author(s)
  鐘方岑，夏井雅典，羽生貴弘
- Organizer
  ICD学生・若手研究会
- Data Source
  KAKENHI-PROJECT-23K21651
[Presentation] A Spintronics-Based Nonvolatile FPGA and Its Application to Edge-AI Accelerator2022
- Author(s)
  D. Suzuki and T. Hanyu
- Organizer
  2022 IEEE 15th Int. Symp. Embedded Multicore/Many-core Systems-on-Chip (MCSoC2022)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21H04868
[Presentation] ビットエラー耐性を活用した省エネルギーニューラルネットワークの構成に関する基礎的考察2022
- Author(s)
  浅野健，佐々木優里，夏井雅典，羽生貴弘
- Organizer
  2022年度電気関係学会東北支部連合講演会
- Data Source
  KAKENHI-PROJECT-21H04868
[Presentation] MTJ ベース量子化ニューラルネットワークハードウェアの書込みエネルギー削減手法に関する研究2022
- Author(s)
  浅野健, 夏井雅典, 羽生貴弘
- Organizer
  2022年度ICD/CAS学生・若手研究会
- Data Source
  KAKENHI-PROJECT-21H04868
[Presentation] Fast Solving Complete 2000-node Optimization Problem Using Sotcahstic-Computing Simulated Annealing2022
- Author(s)
  K. Katsuki, D. Shin, N. Onizawa, and T. Hanyu
- Organizer
  IEEE International Conference on Electrocnis, Circuits & Systems (ICECS) 2022
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21650
[Presentation] 書込みエラー特性に基づく MTJ ベース不揮発レジスタの制御部最適化に関する一検討2022
- Author(s)
  酒井楓，夏井雅典，羽生貴弘
- Organizer
  ICD学生・若手研究会
- Data Source
  KAKENHI-PROJECT-23K21651
[Presentation] Prospects of MTJ-Based Nonvolatile Logic-in-Memory Circuits and Their Applications to AI Hardware2022
- Author(s)
  Takahiro Hanyu
- Organizer
  The 3rd International Symposium on AI and Electronics
- Invited
- Data Source
  KAKENHI-PROJECT-21H04868
[Presentation] Prospects of Energy-Efficient Edge-AI Accelerator Architecture Using Nonvolatile Logic2022
- Author(s)
  M. Natsui, D. Suzuki, Y. Takako, A. Tamakoshi, and T. Hanyu
- Organizer
  2022 International Symposium on Nonlinear Theory and Its Applications (NOLTA2022)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21651
[Presentation] アクセラレータ制御命令を組み込んだRISC-Vベース省エネルギー不揮発CPUの構成2022
- Author(s)
  坂本佳介，夏井雅典，羽生貴弘
- Organizer
  電子情報通信学会集積回路研究会「LSIとシステムのワークショップ」
- Data Source
  KAKENHI-PROJECT-21H04868
[Presentation] Operation-Condition-Aware Dynamic Power Gating for Nonvolatile LSIs2022
- Author(s)
  Fangcen Zhong, Masanori Natsui, and Takahiro Hanyu
- Organizer
  31st International Workshop on Post-Binary ULSI Systems
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21H04868
[Presentation] Design of an Energy-Efficient Nonvolatile Lookup Table Circuit Using Active-Load-Localized Circuitry with Self-Terminated Writing/Reading2022
- Author(s)
  Daisuke Suzuki and Takahiro Hanyu
- Organizer
  2022 International Conference on Solid State Devices and Materials (SSDM 2022)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21H04868
[Presentation] 書込みエラー検出機能を有する高信頼不揮発レジスタの構成2022
- Author(s)
  酒井楓，夏井雅典，羽生貴弘
- Organizer
  2022年度電気関係学会東北支部連合大会
- Data Source
  KAKENHI-PROJECT-23K21651
[Presentation] Operation-Condition-Aware Dynamic Power Gating for Nonvolatile LSIs2022
- Author(s)
  F. Zhong, M. Natsui, and T. Hanyu
- Organizer
  31st International Workshop on Post-Binary ULSI Systems
- Data Source
  KAKENHI-PROJECT-23K21651
[Presentation] Stochastic演算に基づくQMCによるアニーリング処理の高速化2022
- Author(s)
  佐々木遼真, 鬼沢直哉, 羽生貴弘
- Organizer
  2022年度　電気関係学会東北支部連合大会
- Data Source
  KAKENHI-PROJECT-23K21650
[Presentation] Energy-Efficient Nonvolatile RISC-V CPU with a Custom Instruction-Controlled Accelerator2022
- Author(s)
  K. Sakamoto, M. Natsui, and T. Hanyu
- Organizer
  2022 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2022)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21651
[Presentation] アクセラレータ制御命令を組み込んだRISC-Vベース省エネルギー不揮発CPUの構成2022
- Author(s)
  坂本佳介，夏井雅典，羽生貴弘
- Organizer
  LSIとシステムのワークショップ2022
- Data Source
  KAKENHI-PROJECT-23K21651
[Presentation] Design of a Low-Power FPGA-Based CNN Accelerator Based on Nonvolatile Logic-in-Memory Circuitry2022
- Author(s)
  D. Suzuki, M. Natsui, A. Tamakoshi, Y. Takako, and T. Hanyu
- Organizer
  2022 International Symposium on Nonlinear Theory and Its Applications (NOLTA2022)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21651
[Presentation] Design of a Low-Power FPGA-Based CNN Accelerator Based on Nonvolatile Logic-in-Memory Circuitry2022
- Author(s)
  D. Suzuki, M. Natsui, A. Tamakoshi, Y. Takako, and T. Hanyu
- Organizer
  2022 International Symposium on Nonlinear Theory and Its Applications (NOLTA 2022)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21H04868
[Presentation] Challenge of MTJ-Based Nonvolatile Logic-in-Memory Circuits and Their Applications2021
- Author(s)
  Takahiro Hanyu
- Organizer
  16th IEEE/ACM International Symposium on Nanoscale Architectures
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H06300
[Presentation] Dynamic Power-Gating-Switch Control Technique and Its Application to an Energy-Efficient Embedded STT-MRAM2021
- Author(s)
  F. Zhong, M. Natsui, and T. Hanyu
- Organizer
  2021 International Conference on Solid State Devices and Materials (SSDM2021)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21651
[Presentation] Challenge of MTJ-Based Nonvolatile Logic-in-Memory Circuits and Their Applications2021
- Author(s)
  Takahiro Hanyu
- Organizer
  Joint Seminar of BRAIN INSPIRED COMPUTING, PHYSICS, ARCHITECTURES, MATERIALS AND APPLICATIONS (BICPAMA)
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21H04868
[Presentation] Challenge of MTJ-Based Nonvolatile Logic-in-Memory Circuits and Their Applications2021
- Author(s)
  Takahiro Hanyu
- Organizer
  16th IEEE/ACM International Symposium on Nanoscale Architectures
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21H04868
[Presentation] Challenge of MTJ-Based Nonvolatile Logic-in-Memory Circuits and Their Applications2021
- Author(s)
  Takahiro Hanyu
- Organizer
  Joint Seminar of BRAIN INSPIRED COMPUTING, PHYSICS, ARCHITECTURES, MATERIALS AND APPLICATIONS (BICPAMA)
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H06300
[Presentation] 不揮発性ロジックが拓くエッジAIハードウェア・パラダイムの展望2021
- Author(s)
  羽生貴弘
- Organizer
  LSIとシステムのワークショップ2021（電子情報通信学会・集積回路研究会）
- Invited
- Data Source
  KAKENHI-PROJECT-16H06300
[Presentation] Integral Stochastic演算に基づくSimulated Annealing法の高速化2021
- Author(s)
  勝木康太, シントッキュ, 鬼沢直哉, 羽生貴弘
- Organizer
  2021年度電気関係学会東北支部連合大会
- Data Source
  KAKENHI-PROJECT-23K21650
[Presentation] Dynamic Power-Gating-Switch Control Technique and Its Application to an Energy-Efficient Embedded STT-MRAM2021
- Author(s)
  Fangcen Zhong, Masanori Natsui, and Takahiro Hanyu
- Organizer
  2021 International Conference on Solid State Devices and Materials (SSDM)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21H04868
[Presentation] 不揮発性ロジックが拓くエッジAIハードウェア・パラダイムの展望2021
- Author(s)
  羽生貴弘
- Organizer
  LSIとシステムのワークショップ2021（電子情報通信学会・集積回路研究会）
- Invited
- Data Source
  KAKENHI-PROJECT-21H04868
[Presentation] Impact of a nonvolatile multiple-valued circuit technique for energy-efficient binarized neural-network hardware2020
- Author(s)
  Takahiro Hanyu
- Organizer
  ENGE 2020(The 6th International Conference on Electronnic Materials and Nanotechnology for Green Environment)
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H06300
[Presentation] Challenge of Nonvolatile Logic LSI for Edge AI Applications2020
- Author(s)
  Takahiro Hanyu
- Organizer
  U. of A. Research Cluster Forum
- Invited
- Data Source
  KAKENHI-PROJECT-16H06300
[Presentation] 不揮発性ロジックが拓く脳型コンピューティングの挑戦2020
- Author(s)
  羽生貴弘
- Organizer
  第７回電子デバイスフォーラム京都
- Invited
- Data Source
  KAKENHI-PROJECT-16H06300
[Presentation] ポストCMOS回路技術が拓く脳型LSIの挑戦2019
- Author(s)
  羽生隆弘
- Organizer
  日本磁気学会・第6回岩崎コンファランス
- Invited
- Data Source
  KAKENHI-PROJECT-16H06300
[Presentation] Approximate Computing応用高性能マルチコンテキスト(MC-)TCAMの構成2019
- Author(s)
  荒川怜、鬼沢直哉、羽生貴弘
- Organizer
  2019年度　電気関係学会東北支部連合大会
- Data Source
  KAKENHI-PROJECT-16H06300
[Presentation] Multi-Context TCAM Based Selective Computing Architecture for a Low-Paper NN2019
- Author(s)
  Ren Arakawa, Naoya Onizawa, Jean-Philippe Diguet, and Takahiro Hanyu
- Organizer
  26th IEEE International Conference on Electrocnis, Circuits & Systems (ICECS)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H06300
[Presentation] Stochastic computing for brainware LSI2019
- Author(s)
  N. Onizawa, W. J. Gross, and T. Hanyu
- Organizer
  IEEE ASYNC'19 Special Session
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H06300
[Presentation] Minimum Power Supply Asynchronous Circuits for Re-initialization Free Computing2018
- Author(s)
  M. Imai, N. Onizawa, T. Hanyu, and T. Yoneda
- Organizer
  21st Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H06300
[Presentation] ポストCMOS回路技術が拓くAIハードウェアの挑戦2018
- Author(s)
  羽生貴弘
- Organizer
  デザインガイア2018
- Invited
- Data Source
  KAKENHI-PROJECT-16H06300
[Presentation] スピントロニクスが拓く新しいロジックLSIの展望2018
- Author(s)
  羽生貴弘，鈴木大輔，鬼沢直哉，夏井雅典，遠藤哲郎，大野英男
- Organizer
  CSRN年度末シンポジウム
- Invited
- Data Source
  KAKENHI-PROJECT-16H06300
[Presentation] Prospects of Nonvolatile Logic LSI Using MTJ/MOS-Hybrid Circuitry and Its Application2018
- Author(s)
  T. Hanyu
- Organizer
  2018 International Conference on Solid State Devices and Materials (SSDM2018)
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H06300
[Presentation] Design of a Low-Power MTJ-Based True Random Number Generator Using a Multi Voltage/Current Convertor2018
- Author(s)
  S. Mukaida, N. Onizawa, T. Hanyu
- Organizer
  ISMVL2018
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H06300
[Presentation] Challenge of Spintronics-Based Nonvolatile Logic LSI and Its Possibility2018
- Author(s)
  T. Hanyu
- Organizer
  Tohoku/SG-Spin workshop on Spintronics
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H06300
[Presentation] Challenge of an MTJ-Based Non-Volatile Logic LSI for Internet-of-Things Application2018
- Author(s)
  T. Hanyu
- Organizer
  Workshop on Next Generation Computing System
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H06300
[Presentation] Challenge of Spintronic-Device-Based Nonvolatile Logic-in-Memory Architecture for Internet-of-Things Applications2018
- Author(s)
  T. Hanyu
- Organizer
  世界トップレベル研究拠点（材料科学・スピントロニクス）合同キックオフシンポジウム
- Invited
- Data Source
  KAKENHI-PROJECT-16H06300
[Presentation] MTJ-Based Asynchronous Circuits for Re-initialization Free Computing against Power Failures2017
- Author(s)
  N. Onizawa, M. Imai, T. Hanyu, and T. Yoneda
- Organizer
  23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H06300
[Presentation] Three-Terminal MTJ-Based Nonvolatile Logic Circuits with Self-Terminated Writing Mechanism for Ultra-Low-Power VLSI Processor2017
- Author(s)
  T. Hanyu, D. Suzuki, N. Onizawa, and M. Natsui
- Organizer
  Design, Automation & Test in Europe (DATE)
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H06300
[Presentation] A Soft/Write-Error Resilient CMOS/MTJ Nonvolatile Flip-Flop Based on Majority-Decision Shared Writing2016
- Author(s)
  Naoya Onizawa and Takahiro Hanyu
- Organizer
  2016 International Conference on Solid State Devices and Materials (SSDM2016)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H06300
[Presentation] A Self-Terminated Energy-Efficient Nonvolatile Flip-Flop Using 3-terminal Magnetic Tunnel Junction Device2016
- Author(s)
  Daisuke Suzuki and Takahiro Hanyu
- Organizer
  2016 International Conference on Solid State Devices and Materials (SSDM2016)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H06300
[Presentation] Highly Reliable MTJ-Based Motion-Vector Prediction Unit with Dynamic Write Error Masking Scheme2016
- Author(s)
  Masanori Natsui, Akira Tamakoshi, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu
- Organizer
  2016 International Conference on Solid State Devices and Materials (SSDM2016)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H06300
[Presentation] Power-Gated Single-Track Asynchronous Circuits Using Three-Terminal MTJ-Based Nonvolatile Devices for Energy Harvesting Systems2016
- Author(s)
  Tomohiro Yoneda, Naoya Onizawa, Masashi Imai, Takahiro Hanyu,
- Organizer
  Async2016 Fresh ideas track
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H06300
[Presentation] MTJ/MOS-Hybrid Logic-Circuit Design Flow for Nonvolatile Logic-in-Memory LSI2013
- Author(s)
  M. Natsui, N. Sakimura, T. Sugibayashi, and T, Hanyu
- Organizer
  2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)
- Place of Presentation
  Beijing, China
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] MTJ素子を用いた不揮発ロジックLSIの低電力化に関する一考察2013
- Author(s)
  夏井雅典, 荒木敦司, 羽生貴弘
- Organizer
  多値論理研究ノート
- Place of Presentation
  兵庫
- Year and Date
  2013-09-14
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] MTJ 素子を用いた不揮発ロジックLSI の低電力化に関する一考察2013
- Author(s)
  夏井雅典，荒木敦司，羽生貴弘
- Organizer
  第36回多値論理フォーラム
- Place of Presentation
  姫路
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] Design of a Low-Voltage Logic Gate Based on Differential-Pair Circuitry2013
- Author(s)
  K. Kashiuchi, M. Natsui, and T. Hanyu
- Organizer
  2013 International Workshop on Emerging ICT
- Place of Presentation
  Sendai, Japan
- Year and Date
  2013-10-29
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] Design and Evaluation of a Differential Switching Gate for Low-Voltage Applications2013
- Author(s)
  M. Natsui, K. Kashiuchi, and T. Hanyu
- Organizer
  43rd IEEE International Symposium on Multiple-Valued Logic (ISMVL2013)
- Place of Presentation
  Toyama, Japan
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] Design of an MTJ-Based Variation-Resilient Basic Gate of Differential Logic2012
- Author(s)
  Y. Kim, M. Natsui and T. Hanyu
- Organizer
  平成24年度電気関係学会東北支部連合大会
- Place of Presentation
  秋田
- Year and Date
  2012-08-30
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] Vth補償機能を有するMOS/MTJハイブリッド電流モードロジックとその最適化2012
- Author(s)
  キムヨンクン, 夏井雅典, 羽生貴弘
- Organizer
  第25回多値論理とその応用研究会
- Place of Presentation
  宮崎観光ホテル
- Year and Date
  2012-01-08
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] 低電圧動作差動論理基本ゲートの構成に関する一考察2012
- Author(s)
  樫内清弘, 夏井雅典, 羽生貴弘
- Organizer
  多値論理研究ノート
- Place of Presentation
  富山
- Year and Date
  2012-09-15
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] Fundamental Technologies of High-Performance VLSI Processor for Multimedia Applications2012
- Author(s)
  T.Hanyu, M.Natsui, A.Matsumoto
- Organizer
  The 5th International Symposium and The 4th Student-Organizing International Mini-Conference on Information Electronics Systems
- Place of Presentation
  仙台ウエスティンホテル
- Year and Date
  2012-02-23
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] Vth補償機能を有するMOS/MTJハイブリッド電流モードロジックとその最適化2012
- Author(s)
  キムヨンクン, 夏井雅典, 羽生貴弘
- Organizer
  第25回多値論理とその応用研究会
- Place of Presentation
  宮崎
- Year and Date
  2012-01-08
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] 低スイッチング電力基本論理ゲートの構成に関する一考察2012
- Author(s)
  樫内清弘, 夏井雅典, 羽生貴弘
- Organizer
  平成24年度電気関係学会東北支部連合大会
- Place of Presentation
  秋田
- Year and Date
  2012-08-30
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] 可変抵抗素子を用いたポストプロセスばらつき補償機能付きOTAの検討2011
- Author(s)
  長嶋孝晃, 夏井雅典, 桝井昇一, 羽生貴弘
- Organizer
  平成23年度電気関係学会東北支部連合大会
- Place of Presentation
  宮城
- Year and Date
  2011-08-26
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] 不揮発性ロジックインメモリアーキテクチャに基づく高信頼VLSI設計技術2011
- Author(s)
  夏井雅典, 羽生貴弘
- Organizer
  第73回ニューパラダイムコンピューティング研究会
- Place of Presentation
  会津大学
- Year and Date
  2011-07-30
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] 不揮発性可変抵抗素子を用いたLSIパラメータばらつき最小化アルゴリズムの検討2011
- Author(s)
  キムヨンクン, 夏井雅典, 羽生貴弘
- Organizer
  平成23年度電気関係学会東北支部連合大会
- Place of Presentation
  東北学院大学
- Year and Date
  2011-08-26
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] Evaluation of Vth-Variation Effect on Multiple-Valued Current-Mode Circuits2011
- Author(s)
  K. Kashiuchi, M. Natsui, and T. Hanyu
- Organizer
  Proceedings of 2011 China-Korea-Japan Electronics and Communications Conference
- Place of Presentation
  University of Electronic Science and Technology of China, China
- Year and Date
  2011-10-27
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] MTJ素子を用いた完全並列形不揮発TCAMワード回路の構成2011
- Author(s)
  勝俣翠, 松永翔雲, 夏井雅典, 羽生貴弘
- Organizer
  第24回多値論理とその応用研究会
- Place of Presentation
  東北大学
- Year and Date
  2011-01-08
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] 不揮発性ロジックインメモリアーキテクチャが拓く新概念VLSI設計パラダイム2011
- Author(s)
  夏井雅典, 羽生貴弘
- Organizer
  LSIとシステムのワークショップ2011
- Place of Presentation
  北九州国際会議場
- Year and Date
  2011-05-16
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] Evaluation of Vth-Variation Effect on Multiple-Valued Current-Mode Circuits2011
- Author(s)
  K.Kashiuchi, M.Natsui, T.Hanyu
- Organizer
  2011 China-Korea-Japan Electronics and Communications Conference
- Place of Presentation
  中国,成都
- Year and Date
  2011-10-27
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] 不揮発性ロジックインメモリアーキテクチャが拓く新コンピューティングパラダイムの展望2011
- Author(s)
  夏井雅典, 羽生貴弘
- Organizer
  第58回応用物理学関係連合講演会
- Place of Presentation
  神奈川工科大学
- Year and Date
  2011-03-24
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] 不揮発性ロジックインメモリアーキテクチャが拓く新概念VLSI 設計パラダイム2011
- Author(s)
  夏井雅典, 羽生貴弘
- Organizer
  LSI とシステムのワークショップ2011
- Place of Presentation
  福岡
- Year and Date
  2011-05-16
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] 不揮発性可変抵抗素子を用いたLSIパラメータばらつき最小化アルゴリズムの検討2011
- Author(s)
  キムヨンクン, 夏井雅典, 羽生貴弘
- Organizer
  平成23年度電気関係学会東北支部連合大会
- Place of Presentation
  宮城
- Year and Date
  2011-08-26
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] 可変抵抗素子を用いたポストプロセスばらつき補償機能付きOTAの検討2011
- Author(s)
  長嶋孝晃, 夏井雅典, 桝井昇一, 羽生貴弘
- Organizer
  平成23年度電気関係学会東北支部連合大会
- Place of Presentation
  東北学院大学
- Year and Date
  2011-08-26
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] MTJ素子を用いた完全並列形不揮発TCAMワード回路の構成2011
- Author(s)
  勝俣翠, 松永翔雲, 夏井雅典, 羽生貴弘
- Organizer
  第24回多値論理とその応用研究会
- Place of Presentation
  宮城
- Year and Date
  2011-01-08
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] MTJ-Based Nonvolatile Reconfigurable LSI with Fine Grained Power Management2010
- Author(s)
  L.Yuhui, D.Suzuki, M.Natsui, T.Hanyu
- Organizer
  Japan-China-Korea Conference on Electronics & Communications 2010
- Place of Presentation
  東北大学
- Year and Date
  2010-11-01
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] Design of a Dependable Logic Circuit Using Nonvolatile Programmable Devices2010
- Author(s)
  Y. Kim, M. Natsui and T. Hanyu
- Organizer
  Japan-China-Korea Conference on Electronics & Communications 2010
- Place of Presentation
  Tohoku University, Sendai, Japan
- Year and Date
  2010-11-01
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] Fundamental Technologies towards New Paradigm VLSI Computing2010
- Author(s)
  T.Hanyu, M.Natsui, A.Matsumoto, S.Matsunaga, N.Onizawa, D.Suzuki
- Organizer
  The 4th International Symposium on Information Electronics Systems
- Place of Presentation
  仙台エクセルホテル東急
- Year and Date
  2010-07-08
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] 完全並列形不揮発TCAM向けワード回路の構成2010
- Author(s)
  勝俣翠, 松永翔雲, 夏井雅典, 羽生貴弘
- Organizer
  平成22年度電気関係学会東北支部連合大会
- Place of Presentation
  八戸工業大学
- Year and Date
  2010-08-26
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] Process-Variation-Aware VLSI Design Using an Emerging Functional Devices and Its Impact2010
- Author(s)
  M.Natsui, T.Hanyu
- Organizer
  19th International Workshop on Post-Binary ULSI Systems
- Place of Presentation
  スペイン,バルセロナ
- Year and Date
  2010-05-28
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] MTJ-Based Nonvolatile Reconfigurable LSI with Fine Grained Power Management2010
- Author(s)
  L. Yuhui, D. Suzuki, M. Natsui and T. Hanyu
- Organizer
  Japan-China-Korea Conference on Electronics & Communications 2010
- Place of Presentation
  Tohoku University, Sendai, Japan
- Year and Date
  2010-11-01
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] MTJ素子を用いた低消費電力不揮発性TCAMのパワーゲーティング手法2010
- Author(s)
  松永翔雲, 夏井雅典, 羽生貴弘
- Organizer
  多値論理研究ノート
- Place of Presentation
  広島
- Year and Date
  2010-09-11
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] MTJ素子を用いた低消費電力不揮発性TCAMのパワーケーディング手法2010
- Author(s)
  松永翔雲, 夏井雅典, 羽生貴弘
- Organizer
  第33回多値論理フォーラム
- Place of Presentation
  広島市まちづくり市民交流プラザ
- Year and Date
  2010-09-11
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] Design of a Dependable Logic Circuit Using Nonvolatile Programmable Devices2010
- Author(s)
  Y.Kim, M.Natsui, T.Hanyu
- Organizer
  Japan-China-Korea Conference on Electronics & Communications 2010
- Place of Presentation
  東北大学
- Year and Date
  2010-11-01
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] 完全並列形不揮発TCAM向けワード回路の構成2010
- Author(s)
  勝俣翠, 松永翔雲, 夏井雅典, 羽生貴弘
- Organizer
  平成22年度電気関係学会東北支部連合大会
- Place of Presentation
  青森
- Year and Date
  2010-08-26
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] Process-Variation-Aware VLSI Design Using an Emerging Functional Devices and Its Impact2010
- Author(s)
  M. Natsui and T. Hanyu
- Organizer
  Booklet of the 19th International Workshop on Post-Binary ULSI Systems
- Place of Presentation
  Casa Convalescencia, Barcelona, Spain
- Year and Date
  2010-05-28
- Data Source
  KAKENHI-PROJECT-22360137
[Presentation] 多値データ転送に基づく高性能NoCの構成2009
- Author(s)
  松本敦, 羽生貴弘
- Organizer
  電子情報通信学会「多値論理とその応用」第二種研究会技術報告
- Place of Presentation
  桐生
- Year and Date
  2009-01-10
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System2009
- Author(s)
  T. Matsuura, H. Shirahama, M. Natsui and T. Hanyu
- Organizer
  Naha
- Place of Presentation
  Okinawa, Japan
- Year and Date
  2009-05-21
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] 高信頼電流モード多値集積回路技術とその応用2009
- Author(s)
  白濱弘勝, 永井亮, 羽生青弓八
- Organizer
  電子情報通信学会「多値論理とその応用」第二種研究会技術報告
- Place of Presentation
  桐生
- Year and Date
  2009-01-10
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Robust Multiple-Valued Current-Mode Circuit Components Based on Adaptive Reference-Voltage Control2009
- Author(s)
  N. Onizawa and T. Hanyu
- Organizer
  Naha
- Place of Presentation
  Okinawa, Japan
- Year and Date
  2009-05-21
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] 出力状態モニタリングに基づく電流モード多値順序回路の低消費電力化2008
- Author(s)
  松浦貴史, 白濱弘勝, 夏井雅典, 羽生貴弘
- Organizer
  第31回多値論理フォーラム
- Place of Presentation
  沖縄
- Year and Date
  2008-09-12
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Asynchronous data-transfer interface for an interleaver in fully-parallel low-density parity-check decoders2008
- Author(s)
  N. Onizawa and T. Hanyu
- Place of Presentation
  Sendai, Japan
- Year and Date
  2008-10-17
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] 適応的電流源制御に基づくパイプライン電流モード多値演算回路の低電力化2008
- Author(s)
  松浦貴史, 白濱弘勝, 夏井雅典, 羽生貴弘
- Place of Presentation
  沖縄
- Year and Date
  2008-09-12
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Systematic Design and Verification of Binary / Multiple-V alued Fused Logic Circuits2008
- Author(s)
  Takashi Arimitsu, Tasuku Nagai, Masanori Natsui and Takahiro Hanyu
- Organizer
  Proceedings of 2008 China-Korea-Japan Graduates Workshop on Electronic Information
- Place of Presentation
  成都(中国)
- Year and Date
  2008-10-30
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit2008
- Author(s)
  T. Nagai, N. Onizawa and T. Hanyu
- Organizer
  Dallas, TX
- Place of Presentation
  USA
- Year and Date
  2008-05-22
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] MRロジックとその可能性2008
- Author(s)
  羽生貴弘, 松本敦, 松永翔雲
- Organizer
  第55回応用物理関係学会講演会
- Place of Presentation
  千葉
- Year and Date
  2008-03-27
- Data Source
  KAKENHI-PROJECT-18650009
[Presentation] 電流モ-ドsingle-track方式に基づく非同期データ転送の高速化2008
- Author(s)
  大竹遥, 鬼沢直哉, 松本敦, 羽生貴弘
- Place of Presentation
  福島
- Year and Date
  2008-08-22
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] 次世代VLSI向き多値回路の系統的設計2008
- Author(s)
  夏井雅典, 羽生貴弘
- Place of Presentation
  沖縄
- Year and Date
  2008-09-12
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Design of a Processing Element Based on Multiple-Valued Current-Mode Logic for a Many-Core Processor2008
- Author(s)
  H. Shirahama and T. Hanyu
- Place of Presentation
  Sendai, Japan
- Year and Date
  2008-10-17
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Asynchronous Multiple-Valued Data Transfer and Its Application2008
- Author(s)
  T. Funazaki, N. Onizawa, A. Matsumoto and T. Hanyu
- Place of Presentation
  Chengdu, China
- Year and Date
  2008-10-30
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] High-level Synthesis of Asynchronous Circuits and Its Optimization2008
- Author(s)
  A. Matsumoto, T. Yoneda and T. Hanyu
- Organizer
  Optimization, Dallas, TX
- Place of Presentation
  USA
- Year and Date
  2008-05-24
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] 電流モードsingle-track方式に基づく非同期データ転送の高速化2008
- Author(s)
  大竹遥, 鬼沢直哉, 松本敦, 羽生貴弘
- Organizer
  平成20年度電気関係学会東北支部連合大会講演論文集
- Place of Presentation
  郡山
- Year and Date
  2008-08-22
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices2008
- Author(s)
  A. Hirosaki, M. Miura, A. Matsumoto and T. Hanyu
- Organizer
  Dallas, TX
- Place of Presentation
  USA
- Year and Date
  2008-05-22
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Systematic Design and Verification of Binary/Multiple-Valued Fused Logic Circuits2008
- Author(s)
  T. Arimitsu, T. Nagai, M. Natsui and T. Hanyu
- Place of Presentation
  Chengdu, China
- Year and Date
  2008-10-30
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Design of High-Performance Quaternary Adders Based on Output-Generator Sharing2008
- Author(s)
  H. Shirahama and T. Hanyu
- Organizer
  Proceedings 38th IEEE International Symposium on Multiple-Valued Logic
- Place of Presentation
  ダラス(アメリカ)
- Year and Date
  2008-05-21
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] 多値符号化に基づく非同期式転送方式の検討2008
- Author(s)
  松本敦, 羽生貴弘
- Organizer
  電子情報通信学会「多値論理とその応用」第二種研究会
- Place of Presentation
  神戸
- Year and Date
  2008-01-13
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] 多値符号化に基づく非同期式転送方式の検討2008
- Author(s)
  松本敦, 羽生貴弘
- Place of Presentation
  兵庫
- Year and Date
  2008-01-13
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Design of High-Performance Quaternary Adders Based on Output-Generator Sharing2008
- Author(s)
  H. Shirahama and T. Hanyu
- Organizer
  Dallas, TX
- Place of Presentation
  USA
- Year and Date
  2008-05-22
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Asynchronous Multiple-Valued Data Transfer and Its Application2008
- Author(s)
  Tomoyoshi Funazaki, Naoya Onizawa, Atsushi Matsumoto and Takahiro Hanyu
- Organizer
  Proceedings of 2008 China-Korea-Japan Graduates Workshop on Electronic Information
- Place of Presentation
  成都(中国)
- Year and Date
  2008-10-30
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] 出力状態モニタリングに基づく電流モード多値順序回路の低消費電力化2008
- Author(s)
  松浦貴史, 白濱弘勝, 夏井雅典, 羽生貴弘
- Organizer
  平成20年度電気関係学会東北支部連合大会講演論文集
- Place of Presentation
  郡山
- Year and Date
  2008-08-22
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Asynchronous Data-Transfer Interface for an Interleaver in Fully-Parallel Low-Density Parity-Check Decoders2008
- Author(s)
  Naoya Onizawa and Takahiro Hanyu
- Organizer
  Proceedings of the 1st Student Organizing International Mini-Conference on Information Electronics Systems
- Place of Presentation
  仙台
- Year and Date
  2008-10-16
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] 電流モード多値回路および電圧モード多値回路の構成と評価2008
- Author(s)
  白濱弘勝, 羽生貴弘
- Organizer
  電子情報通信学会「多値論理とその応用」第二種研究会
- Place of Presentation
  神戸
- Year and Date
  2008-01-13
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] 出力状態モニタリングに基づく電流モード多値順序回路の低消費電力化2008
- Author(s)
  松浦貴史, 白濱弘勝, 夏井雅典, 羽生貴弘
- Place of Presentation
  福島
- Year and Date
  2008-08-22
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] TMRロジックとその応用2008
- Author(s)
  羽生貴弘
- Organizer
  日本磁気学会第159回研究会
- Place of Presentation
  東京
- Year and Date
  2008-03-03
- Data Source
  KAKENHI-PROJECT-18650009
[Presentation] 電流モード多値回路および電圧モード多値回路の構成と評価2008
- Author(s)
  白濱弘勝, 羽生貴弘
- Place of Presentation
  兵庫
- Year and Date
  2008-01-13
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] 3.2-Gb/s 1024-b Rate-1/2 LDPC Decoder Chip Using a Flooding-Type Update-Schedule Algorithm2007
- Author(s)
  N. Onizawa, T. Ikeda, T. Hanyu and V. C. Gaudet
- Place of Presentation
  Montreal, Canada
- Year and Date
  2007-08-05
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Quaternary Processing Element for a Multi-Core VLSI processor2007
- Author(s)
  H. Shirahama, T. Hanyu, M. Nakajima, A. Mochizuki, and K. Arimoto
- Organizer
  4th International Workshop of Tohoku Univ. and Yeungnum Univ.
- Place of Presentation
  松島
- Year and Date
  2007-11-12
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Implementation of a High-Throughput LDPC Decoder Chip Using an Asynchronous Interleaving Scheme2007
- Author(s)
  N. Onizawa and T. Hanyu
- Place of Presentation
  Sendai, Japan
- Year and Date
  2007-01-25
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] 多値非同期データ転送方式に基づく高性能LDPCデコーダLSIの実現2007
- Author(s)
  鬼沢直哉, 羽生貴弘, V. Gaudet
- Organizer
  第11回システムLSIワークショップ
- Place of Presentation
  小倉
- Year and Date
  2007-11-20
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] 多値電流モード非同期データ転送方式に基づくLDPCデコーダLSIの実現2007
- Author(s)
  鬼沢直哉, 羽生貴弘
- Place of Presentation
  愛知
- Year and Date
  2007-03-21
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] 多値非同期データ転送方式に基づく高性能LDPCデコーダLSIの実現2007
- Author(s)
  鬼沢直哉, 羽生貴弘, Vincent Gaudet
- Place of Presentation
  福岡
- Year and Date
  2007-11-20
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Asynchronous Peer-to-Peer Simplex/Duplex-Compatible Communication System Using a One-Phase Signaling Scheme2007
- Author(s)
  T. Takahashi, K. Mizusawa, and T. Hanyu
- Organizer
  37th IEEE International Symposium on Multiple-Valued Logic
- Place of Presentation
  オスロ(ノルウェー)
- Year and Date
  2007-05-16
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] 超並列プロセッサ内多値データ転送方式2007
- Author(s)
  白濱弘勝, 羽生貴弘, 中島雅美, 望月明, 有本和民
- Organizer
  多値論理研究会
- Place of Presentation
  湘南
- Year and Date
  2007-08-22
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] 超並列プロセッサ内多値データ転送方式2007
- Author(s)
  白濱弘勝, 羽生貴弘, 中島雅美, 望月明, 有本和民
- Place of Presentation
  神奈川
- Year and Date
  2007-08-21
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] 電流モード多値回路の高速動作検証手法2007
- Author(s)
  永井亮, 鬼沢直哉, 羽生貴弘
- Organizer
  平成19年度電気関係学会東北支部連合大会
- Place of Presentation
  弘前
- Year and Date
  2007-08-24
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] 3.2-Gb/s 1024-b Rate-1/2 LDPC Decoder Chip Using a Flooding-Type Update-Schedule Algorithm2007
- Author(s)
  N. Onizawa, T. Ikeda, T. Hanyu, and V. Gaudet
- Organizer
  50th IEEE Midwest Symposium on Circuits and Systems
- Place of Presentation
  モントリオール(カナダ)
- Year and Date
  2007-08-06
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Design and Evaluation of a Multiple-Valued Full Adder2007
- Author(s)
  T. Matsuura, H. Shirahama, T. Hanyu
- Place of Presentation
  Sendai, Japan
- Year and Date
  2007-11-12
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] 電流モード多値回路の信頼性評価2007
- Author(s)
  高橋知宏, 羽生貴弘
- Place of Presentation
  愛知
- Year and Date
  2007-03-20
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] High-speed Asynchronous Data Transfer Scheme Based on One-Phase Dual-Rail Coding2007
- Author(s)
  Y. Otake, K. Mizusawa, N. Onizawa and T. Hanyu
- Place of Presentation
  Sendai, Japan
- Year and Date
  2007-11-12
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Standby-Power-Free Logic-in-Memory Circuit Based on Ferroelectric Logic2007
- Author(s)
  S. Matsunaga, T. Hanyu, H. Kimura, Y. Fujimori, M. Moriwake, and H. Takasu
- Organizer
  Proc. 4th International Workshop of Tohoku Univ. and Yeungnum Univ
- Place of Presentation
  松島
- Year and Date
  2007-11-12
- Data Source
  KAKENHI-PROJECT-18650009
[Presentation] Active-Load Differential Comparator for Crosstalk-Noise Reduction2007
- Author(s)
  A. Mochizuki, M. Miura and T. Hanyu
- Place of Presentation
  Oslo, Norway
- Year and Date
  2007-05-15
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] 非同期式回路のFPGA実現とその評価2007
- Author(s)
  松本敦, 米田友洋, 羽生貴弘
- Place of Presentation
  北海道
- Year and Date
  2007-08-02
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Novel Circuit Techniques for High-Speed Intra-Chip Communication2007
- Author(s)
  T. Hanyu, T. Takahashi and S. Matsunaga
- Place of Presentation
  Sendai, Japan
- Year and Date
  2007-01-23
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Asynchronous Peer-to-Peer Simplex/ Duplex-Compatible Communication System Using a One-Phase Signaling Scheme2007
- Author(s)
  T. Takahashi, K. Mizusawa and T. Hanyu
- Place of Presentation
  Oslo, Norway
- Year and Date
  2007-05-15
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor2007
- Author(s)
  H. Shirahama, A. Mochizuki, T. Hanyu, M. Nakajima and K. Arimoto
- Place of Presentation
  Oslo, Norway
- Year and Date
  2007-05-15
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] High-speed Asynchronous Data Transfer Scheme Based on One-Phase Dual-Rail Coding2007
- Author(s)
  Y. Otake, K. Mizusawa, N. Onizawa, and T. Hanyu
- Organizer
  4th International Workshop of Tohoku Univ. and Yeungnum Univ.
- Place of Presentation
  松島
- Year and Date
  2007-11-12
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] A Standby-Power-Free TCAM Based on TMR Logic2007
- Author(s)
  Kei Kimura and Takahiro Hanyu
- Organizer
  Proc. 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS)
- Place of Presentation
  モントリオール(カナダ)
- Year and Date
  2007-08-07
- Data Source
  KAKENHI-PROJECT-18650009
[Presentation] 非同期式回路のFPGA実現とその評価2007
- Author(s)
  松本敦, 米田友洋, 羽生貴弘
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  旭川
- Year and Date
  2007-08-02
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Active-Load Differential Comparator for Crosstalk-Noise Reduction2007
- Author(s)
  A. Mochizuki, M. Miura, and T. Hanyu
- Organizer
  37th IEEE International Symposium on Multiple-Valued Logic
- Place of Presentation
  オスロ(ノルウェー)
- Year and Date
  2007-05-16
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Design and Evaluation of a Multiple-Valued Full Adder2007
- Author(s)
  T. Matsuura, H. Shirahama, T. Hanyu
- Organizer
  4th International Workshop of Tohoku Univ. and Yeungnum Univ.
- Place of Presentation
  松島
- Year and Date
  2007-11-12
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Implementation of an Asynchronous LDPC Decoder Using Multiple-Valued Duplex Interleaving2007
- Author(s)
  N. Onizawa, T. Hanyu, and V. Gaudet
- Organizer
  The 2007 Analog Decoding Workshop
- Place of Presentation
  モントリオール(カナダ)
- Year and Date
  2007-05-24
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Quaternary Processing Element for a Multi-Core VLSI processor2007
- Author(s)
  H. Shirahama, T. Hanyu, M. Nakajima, A. Mochizuki and K. Arimoto
- Place of Presentation
  Sendai, Japan
- Year and Date
  2007-11-12
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] 電流モード多値回路の高速動作検証手法2007
- Author(s)
  永井亮, 鬼沢直哉, 羽生貴弘
- Place of Presentation
  青森
- Year and Date
  2007-08-24
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor2007
- Author(s)
  H. Shirahama, A. Mochizuki, T. Hanyu, M. Nakajima, K. Arimoto
- Organizer
  37th IEEE International Symposium on Multiple-Valued Logic
- Place of Presentation
  オスロ(ノルウェー)
- Year and Date
  2007-05-16
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Implementation of an Asynchronous LDPC Decoder Using Multiple-Valued Duplex Interleaving2007
- Author(s)
  N. Onizawa, T. Hanyu and V. Gaudet
- Place of Presentation
  Montreal, Canada
- Year and Date
  2007-05-24
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] TMR素子を用いたVthばらつき補正可能MOS基本回路とその応用2007
- Author(s)
  廣崎旭宏, 三浦成友, 羽生貴弘
- Organizer
  平成19年度電気関係学会東北支部連合大会
- Place of Presentation
  弘前
- Year and Date
  2007-08-24
- Data Source
  KAKENHI-PROJECT-18650009
[Presentation] A Simplex/Duplex-Compatible System for Asynchronous Peer-to-Peer Communication Using One-phase Signaling2007
- Author(s)
  T. Takahashi and T. Hanyu
- Place of Presentation
  Sendai, Japan
- Year and Date
  2007-01-25
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] A TMR-Based Logic Circuit for a Power-Aware VLSI System2007
- Author(s)
  K. Hiyama, S. Matsunaga, K. Kimura and T. Hanyu
- Organizer
  Proc. 4th International Workshop of Tohoku Univ. and Yeungnum Univ
- Place of Presentation
  松島
- Year and Date
  2007-11-12
- Data Source
  KAKENHI-PROJECT-18650009
[Presentation] 隣接データの類似性に着目した高速LDPC復号化とその評価2006
- Author(s)
  池田智和, 鬼沢直哉, 羽生貴弘
- Place of Presentation
  秋田
- Year and Date
  2006-09-01
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] 多値2線符号化に基づく双方向非同期データ転送LSIの高性能化2006
- Author(s)
  水澤一泰, 高橋知宏, 羽生貴弘
- Place of Presentation
  秋田
- Year and Date
  2006-09-01
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] 2線差動論理に基づくノイズフリー多値集積回路2006
- Author(s)
  三浦成友, 望月明, 羽生貴弘
- Place of Presentation
  秋田
- Year and Date
  2006-09-01
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Highly Reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic2006
- Author(s)
  A. Mochizuki and T. Hanyu
- Place of Presentation
  Singapore
- Year and Date
  2006-05-18
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Design of a Microprocessor Data Path Using Four-Valued Differential-Pair Circuits2006
- Author(s)
  A. Mochizuki, T. Kitamura, H. Shirahama and T. Hanyu
- Place of Presentation
  Singapore
- Year and Date
  2006-05-18
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] 差動ロジックに基づく高性能VLSIの展望2006
- Author(s)
  望月明, 羽生貴弘
- Place of Presentation
  宮城
- Year and Date
  2006-08-23
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] 多値2線符号化に基づく高性能非同期データ転送VLSI2006
- Author(s)
  高橋知宏, 水澤一泰, 羽生貴弘
- Place of Presentation
  宮城
- Year and Date
  2006-10-27
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Low-power Latch Based on Dynamic Differential Logic2006
- Author(s)
  H. Shirahama, A. Mochizuki, T. Hanyu
- Place of Presentation
  Gyeongju, Korea
- Year and Date
  2006-11-17
- Data Source
  KAKENHI-PROJECT-18300012
[Presentation] Automatic Place and Route Scheme in Multiple-Valued Current-Mode Circuit Design2006
- Author(s)
  T. Nagai, T. Takahashi, N. Onizawa and T. Hanyu
- Place of Presentation
  Gyeongju, Korea
- Year and Date
  2006-11-17
- Data Source
  KAKENHI-PROJECT-18300012

1. KAMEYAMA Michitaka (70124568)

# of Collaborated Projects: 12 results

# of Collaborated Products: 0 results
2. YONEDA Tomohiro (30182851)

# of Collaborated Projects: 5 results

# of Collaborated Products: 4 results
3. NATSUI Masanori (10402661)

# of Collaborated Projects: 5 results

# of Collaborated Products: 93 results
4. MOCHIZUKI Akira (40359542)

# of Collaborated Projects: 4 results

# of Collaborated Products: 24 results
5. 今井雅 (70323665)

# of Collaborated Projects: 4 results

# of Collaborated Products: 4 results
6. HIGUCHI Tatsuo (20005317)

# of Collaborated Projects: 3 results

# of Collaborated Products: 0 results
7. HARIYAMA Masanori (10292260)

# of Collaborated Projects: 3 results

# of Collaborated Products: 0 results
8. 鬼沢直哉 (90551557)

# of Collaborated Projects: 3 results

# of Collaborated Products: 32 results
9. MATSUMOTO Atsushi (40455853)

# of Collaborated Projects: 2 results

# of Collaborated Products: 12 results
10. SMITH Kenneth C.

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
11. SASAO Tsutomu (20112013)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
12. XIAOWEI Deng (70261576)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
13. KIMURA Hiromitsu (00361155)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
14. 川人祥二 (40204763)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
15. 吉瀬謙二 (50323887)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
16. 齋藤寛 (50361671)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
17. 池田正二 (90281865)

# of Collaborated Projects: 1 results

# of Collaborated Products: 2 results
18. 村口正和 (90386623)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
19. BUTLER Jon T.

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
20. LIN H.C.

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
21. NG Wai-Tung

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
22. GULAK Glenn

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
23. SILIO Charle

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
24. SILIO Carles B.

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
25. CHARLES B Si

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
26. JON T Butler

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
27. KENNETH C Sm

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
28. NG Wai Tung

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
29. SMITH Rennet

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
30. 鈴木大輔

# of Collaborated Projects: 0 results

# of Collaborated Products: 1 results

HANYU Takahiro 羽生 貴弘

Hanyu Takahiro 羽生 貴弘

HANYU TAKAHIRO 羽生 貴弘

羽生 貴広 ハニュウ タカヒロ

Research Projects

Research Products

Co-Researchers

Development of a high-speed and ultra-low-power die-hard logic LSI fundamental technology for IoT applicationsPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Review Section

Research Institution

Principal Investigator

Project Period (FY)

Research Category

Review Section

Research Institution

Principal Investigator

Project Period (FY)

Research Category

Review Section

Research Institution

脳型コンピューティング向けダーク・シリコンロジックLSIの基盤技術開発Principal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Fundamental Technology Development of Dark-Silicon Logic LSI for Brain-Inspired ComputingPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Nonvolatile-device-based PVT-variation-resilient VLSI systemPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Implementation of a High-Speed LDPC Decoder LSI Based on a Multiple-Valued Full-Duplex Data-Transfer TechniquePrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

不揮発性デバイスに基づくクイックオンVLSIシステムの構成Principal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Implementation of a High-Speed Asynchronous Data Transfer VLSI Based on Bidirectional Current-Mode Multiple-Valued Circuit TechniquesPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

多値技術に基づく高速データ転送とそのマルチメディアVLSIプロセッサへの応用Principal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Implementation of a Transfer-Bottleneck-Free Multiple-Valued Logic-in-Memory VLSI and Its ApplicationPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Principal Investigator

Project Period (FY)

Research Category

Research Field

HANYU Takahiro 羽生貴弘

Hanyu Takahiro 羽生貴弘

HANYU TAKAHIRO 羽生貴弘

羽生貴広ハニュウタカヒロ