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MOCHIZUKI Akira  望月 明

ORCIDConnect your ORCID iD *help
Researcher Number 40359542
Other IDs
External Links
Affiliation (based on the past Project Information) *help 2008: 東北大学, 電気通信研究所, 助教
2003 – 2006: 東北大学, 電気通信研究所, 助手
Review Section/Research Field
Principal Investigator
Computer system/Network
Except Principal Investigator
Computer system/Network / 計算機科学
Keywords
Principal Investigator
データ密度 / 分散制御方式 / 多値コーディング技術 / パケット通信プロトコル / バス集中管理制御方式 / 時分割制御 / チップ内配線問題 / ダイレクト・メモリ・アクセス / マイクロプロセッサ / フリップフロップ … More / ラッチ / シュミット・トリガ / ノイズ / クロストーク / 差動ロジック / クロストークノイズ / 低消費電力 / 電流源 / 動的制御 / ダイナミック論理 / 差動増幅器 / 電流モード回路 … More
Except Principal Investigator
情報システム / 情報通信工学 / multiple-valued encoding / intra-chip high-speed signaling / network-on-chip / system-on-chip / semiconductor ultra-scaling / equipments / electronic devices / information communication engineering / information system / デュプレックス / プロトコル / 2線式 / チップ内通信 / 双方向同時通信 / 非同期通信プロトコル / 2線符号化方式 / クロックスキュー / クロック分配 / ハンドシェイク通信 / 多値符号化 / チップ内高速データ転送技術 / ネットワークオンチップ / システムオンチップ / 半導体超微細化 / 電子デバイス・機器 / data-transfer bottleneck / operation merging / storage / resistor-circuit network / device modeling / fully parallel processing / ferroelectric capacitor / TMR device / multiple-valued logic-in-memory / 多値基本演算子 / マイクロ順序動作 / ゲートレベルパイプライン処理 / パイプライン乗算器 / 多値集積回路 / フローティングゲートMOSトランジスタ / ゲートレベルパイプライン / FPGA / 不揮発性ロジック / 強誘電体CAM / 相補的動作 / 非破壊読出し / デバイスモデル / 全加算器 / 強誘電体デバイス / 非数値データ処理 / データ転送ボトルネックフリー / 記憶・演算一体化 / 抵抗回路網 / デバイスモデリング / 超並列演算 / 強誘電体キャパシタ / TMR素子 / 多値ロジックインメモリ / ロジック回路 / 不揮発性 / CAM / 低電力化技術 / 超並列処理 / 先端機能デバイス / 高速プロトタイピング / 非同期式制御 / 複号化 / 符号化 / 高速伝送技術 / LDPC符号 / 2線符号 / 非同期通信 / 多値VLSI技術 / 誤り訂正符号 / 高速伝送回路 / 情報機器 Less
  • Research Projects

    (5 results)
  • Research Products

    (73 results)
  • Co-Researchers

    (5 People)
  •  Implementation of a High-Speed LDPC Decoder LSI Based on a Multiple-Valued Full-Duplex Data-Transfer Technique

    • Principal Investigator
      HANYU Takahiro
    • Project Period (FY)
      2006 – 2008
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      Computer system/Network
    • Research Institution
      Tohoku University
  •  不揮発性デバイスに基づくクイックオンVLSIシステムの構成

    • Principal Investigator
      羽生 貴弘
    • Project Period (FY)
      2006 – 2007
    • Research Category
      Grant-in-Aid for Exploratory Research
    • Research Field
      Computer system/Network
    • Research Institution
      Tohoku University
  •  パケット通信に基づくチップ内高速多値データ転送VLSIの開発Principal Investigator

    • Principal Investigator
      望月 明
    • Project Period (FY)
      2004 – 2006
    • Research Category
      Grant-in-Aid for Young Scientists (B)
    • Research Field
      Computer system/Network
    • Research Institution
      Tohoku University
  •  Implementation of a High-Speed Asynchronous Data Transfer VLSI Based on Bidirectional Current-Mode Multiple-Valued Circuit Techniques

    • Principal Investigator
      HANYU Takahiro
    • Project Period (FY)
      2003 – 2005
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      Computer system/Network
    • Research Institution
      Tohoku University
  •  Implementation of a Transfer-Bottleneck-Free Multiple-Valued Logic-in-Memory VLSI and Its Application

    • Principal Investigator
      HANYU Takahiro
    • Project Period (FY)
      2001 – 2004
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      計算機科学
    • Research Institution
      Tohoku University

All 2007 2006 2005 2004

All Journal Article Presentation

  • [Journal Article] Design and Evaluation of a 54x54-bit Multiplier Based on Differential-Pair Circuitry2007

    • Author(s)
      A. Mochizuki, H. Shirahama and T. Hanyu
    • Journal Title

      IEICE Trans. on Electronics Vol.E90-C, No.4

      Pages: 683-691

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] Design and Evaluation of a 54x54-bit Multiplier Based on Differential-Pair Circuitry2007

    • Author(s)
      Akira Mochizuki, Hirokatsu Shirahama and Takahiro Hanyu
    • Journal Title

      IEICE Trans. on Electronics E90-C・4

      Pages: 683-691

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] Highly Reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic2006

    • Author(s)
      Akira Mochizuki
    • Journal Title

      Proc. IEEE International Symposium on Multiple-Valued Logic 36(CD-ROM)

    • Data Source
      KAKENHI-PROJECT-16700045
  • [Journal Article] Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits2006

    • Author(s)
      Akira Mochizuki
    • Journal Title

      Proc. IEEE International Symposium on Multiple-Valued Logic 36(CD-ROM)

    • Data Source
      KAKENHI-PROJECT-16700045
  • [Journal Article] 2線差動論理に基づくノイズフリー多値集積回路2006

    • Author(s)
      三浦 成友, 望月 明, 羽生 貴弘
    • Journal Title

      平成18年度電気関係学会東北支部連合大会講演論文集

      Pages: 341-341

    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] TMR-Based Differential Logic for Vt-Variation Compansation2006

    • Author(s)
      A.Hirosaki, M.Miura, A.Mochizuki, T.Hanyu
    • Journal Title

      Proc. 3rd Workshop of Yeungnum Univ. and Tohoku Univ.

      Pages: 51-52

    • Data Source
      KAKENHI-PROJECT-18650009
  • [Journal Article] 差動ロジックに基づく高性能VLSIの展望2006

    • Author(s)
      望月明, 羽生貴弘
    • Journal Title

      多値論理研究ノート 29

    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic2006

    • Author(s)
      A.Mochizuki, T.Hanyu
    • Journal Title

      Proc. 36th IEEE International Symposium on Multiple-Valued Logic 36(CD-ROM版のため頁番号なし)

    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits2006

    • Author(s)
      A.Mochizuki, T.Kitamura, H.Shirahama, T.Hanyu
    • Journal Title

      Proc. 36th IEEE International Symposium on Multiple-Valued Logic 36(CD-ROM版のため頁番号なし)

    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] Low-power Latch Based on Dynamic Differential Logic2006

    • Author(s)
      H.Shirahama, A.Mochizuki, T.Hanyu
    • Journal Title

      Proc. 3rd Workshop of Yeungnum Univ. and Tohoku Univ 3

      Pages: 138-140

    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic2006

    • Author(s)
      A.Mochizuki, H.Shirahama, T.Hanyu
    • Journal Title

      IEICE Trans. on Electronics E89-C・11

      Pages: 1575-1580

    • NAID

      110007538696

    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic2006

    • Author(s)
      A. Mochizuki, H. Shirahama and T. Hanyu
    • Journal Title

      IEICE Trans. on Electronics Vol.E89-C, No.11

      Pages: 1575-1580

    • NAID

      110007538696

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] TMRロジックとその応用2006

    • Author(s)
      羽生貴弘, 望月明, 渡邊康広
    • Journal Title

      応用電子物性分科会誌 12・4

      Pages: 154-159

    • NAID

      10024270241

    • Data Source
      KAKENHI-PROJECT-18650009
  • [Journal Article] 差動ロジックに基づく高性能VLSIの展望2006

    • Author(s)
      望月 明
    • Journal Title

      多値論理研究ノート 29

    • Data Source
      KAKENHI-PROJECT-16700045
  • [Journal Article] Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic2005

    • Author(s)
      A.Mochizuki
    • Journal Title

      Journal of Multiple-Valued Logic and Soft Computing 11, 5-6

      Pages: 481-498

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic2005

    • Author(s)
      A.Mochizuki
    • Journal Title

      IEEE Journal of Multiple-Valued Logic and Soft Computing 11

      Pages: 481-498

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] A 1.88ns 54x54-bit Multiplier in 0.18μm CMOS Based on Multiple-Valued Differential-Pair Circuitry2005

    • Author(s)
      A.Mochizuki
    • Journal Title

      2005 Symposium on VLSI Circuits, Digest of Technical Papers

      Pages: 264-267

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] 0.2V-Swing Multiple-Valued Differential-Pair Circuit and Its Application to Arithmetic VLSI2005

    • Author(s)
      Akira Mochizuki
    • Journal Title

      14th International Workshop on Post-Binary ULSI Systems 14

      Pages: 35-41

    • Data Source
      KAKENHI-PROJECT-16700045
  • [Journal Article] TMR-Based Logic-in-Memory Circuit for Low-Power VLSI2005

    • Author(s)
      Akira Mochizuki
    • Journal Title

      IEICE Transactions on Fundamentals. (印刷中)(to be published)

    • Data Source
      KAKENHI-PROJECT-13558026
  • [Journal Article] Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic2005

    • Author(s)
      Akira Mochizuki
    • Journal Title

      Journal of Multiple-Valued Logic and Soft Computing (to be published)(印刷中)

    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] 電流モード多値回路技術の展望2005

    • Author(s)
      望月 明
    • Journal Title

      多値論理研究ノート 28

    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] 0.2V-Swing Multiple-Valued Differential-Pair Circuit and Its Application to Arithmetic VLSI2005

    • Author(s)
      Akira Mochizuki
    • Journal Title

      International Workshop on Post-Binary ULSI Systems 14

      Pages: 35-41

    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic2005

    • Author(s)
      Akira Mochizuki
    • Journal Title

      Journal of Multiple-Valued Logic and Soft Computing 11・5-6

      Pages: 481-498

    • Data Source
      KAKENHI-PROJECT-16700045
  • [Journal Article] O.2V-Swing Multiple-Valued Differential-Pair Circuit and Its Application to Arithmetic VLSI2005

    • Author(s)
      A.Mochizuki
    • Journal Title

      International Workshop on Post-Binary ULSI Systems 14

      Pages: 35-41

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] 多値差動ロジックに基づく高性能部分積生成回路の構成2005

    • Author(s)
      望月明
    • Journal Title

      電子情報通信学会2005年総合大会講演論文集

    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic2005

    • Author(s)
      Akira Mochizuki
    • Journal Title

      Journal of Multiple-Valued Logic and Soft Computing 11・5-6

      Pages: 481-498

    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic2005

    • Author(s)
      Akira Mochizuki
    • Journal Title

      J.Multiple-Valued Logic & Soft Computing (採録決定)(印刷中)

    • Data Source
      KAKENHI-PROJECT-16700045
  • [Journal Article] 0.2V-Swing Multiple-Valued Differential-Pair Circuit and Its Application to Arithmetic VLSI2005

    • Author(s)
      A.Mochizuki
    • Journal Title

      International Workshop on Post-Binary ULSI Systems 14

      Pages: 35-41

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] 電流モード多値回路技術の展望2005

    • Author(s)
      望月 明
    • Journal Title

      多値論理研究ノート 28

    • Data Source
      KAKENHI-PROJECT-16700045
  • [Journal Article] A 1.88ns 54x54-bit Multiplier in 0.18μm CMOS Based on Multiple-Valued Differential-Pair Circuitry2005

    • Author(s)
      A.Mochizuki
    • Journal Title

      2005 Symposium on VLSI Circuits

      Pages: 264-267

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] A 1.88ns 54×54-bit Multiplier in 0.18μm CMOS Based on Multiple-Valued Differential-Pair Circuitry2005

    • Author(s)
      Akira Mochizuki
    • Journal Title

      2005 Sympsium on VLSI Circuits, Digest of Technical Papers (to be published)(印刷中)

    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] A 1.88ns 54x54-bit Multiplier in 0.18μm CMOS Based on Multiple-Valued Differential-Pair Circuitry2005

    • Author(s)
      Akira Mochizuki
    • Journal Title

      2005 Symposium on VLSI Circuits, Digest of Technical Papers

      Pages: 264-267

    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] A 1.88ns 54x54-bit Multiplier in 0.18μm CMOS Based on Multiple-Valued Differential-Pair Circuitry2005

    • Author(s)
      Akira Mochizuki
    • Journal Title

      Symposium on VLSI Circuits

      Pages: 264-267

    • Data Source
      KAKENHI-PROJECT-16700045
  • [Journal Article] Low-Power Motion-Vector Detection VLSI Processor Based on Pass-Gate Logic with Dynamic Supply-Voltage/Clock-Frequency Scaling2004

    • Author(s)
      A.Mochizuki
    • Journal Title

      IEICE Trans.on Electronics E87-C,11

      Pages: 1876-1883

    • NAID

      110003214804

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] 多値2線差動論理に基づく高性能算術演算VLSI2004

    • Author(s)
      望月 明
    • Journal Title

      多値論理フォーラム,多値論理研研究ノート 27

    • Data Source
      KAKENHI-PROJECT-16700045
  • [Journal Article] Low-Power Pipelined VLSI System Using a Power-Supply-Controlled CMOS Pass-Gate Network and Its Application2004

    • Author(s)
      Akira Mochizuki
    • Journal Title

      The 2004 International Conference on Circuits/Systems, Computers and Communications

    • Data Source
      KAKENHI-PROJECT-16700045
  • [Journal Article] Low-Power Multiple-Valued Current-Mode Logic Using Substrate Bias Control2004

    • Author(s)
      Akira Mochizuki
    • Journal Title

      IEICE Trans.on Electronics E87-C・4

      Pages: 582-588

    • NAID

      110003214894

    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] Low-Power Multiple-Valued Current-Mode Logic Using Substrate Bias Control2004

    • Author(s)
      Akira Mochizuki
    • Journal Title

      IEICE Trans.on Electronics E87-C,4

      Pages: 582-588

    • NAID

      110003214894

    • Data Source
      KAKENHI-PROJECT-16700045
  • [Journal Article] Dynamically Function-Programmable Bus Architecture for High-Throughput Intra-Chip Data Transfer2004

    • Author(s)
      Akira Mochizuki
    • Journal Title

      IEICE Trans.on Electronics E87-C,11

      Pages: 1915-1922

    • NAID

      110003214810

    • Data Source
      KAKENHI-PROJECT-16700045
  • [Journal Article] Low-Power Motion-Vector Detection VLSI Processor Based on Pass-Gate Logic with Dynamic Supply-Voltage/Clock-Frequency Scaling2004

    • Author(s)
      Akira Mochizuki
    • Journal Title

      IEICE Trans.on Electronics E87-C,11

      Pages: 1876-1883

    • NAID

      110003214804

    • Data Source
      KAKENHI-PROJECT-16700045
  • [Journal Article] Dynamically Function-Programmable Bus Architecture for High-Throughput Intra-Chip Data Transfer2004

    • Author(s)
      Akira Mochizuki
    • Journal Title

      IEICE Trans.on Electronics E87-C・11

      Pages: 1915-1922

    • NAID

      110003214810

    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] 多値2線差動論理に基づく高性能算術演算VLSI2004

    • Author(s)
      望月明
    • Journal Title

      多値論理研究ノート 27

    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] Dynamically Function-Programmable Bus Architecture for High-Throughput Infra-Chip Data Transfer2004

    • Author(s)
      A.Mochizuki
    • Journal Title

      IEICE Trans.on Electronics E87-C, 11

      Pages: 1915-1922

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] Low-Power Multiple-Valued Current-Mode Logic Using Substrate Bias Control2004

    • Author(s)
      A.Mochizuki
    • Journal Title

      IEICE Trans.on Electronics E87-C, 4

      Pages: 582-588

    • NAID

      110003214894

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] TMR-Based Logic-in-Memory Circuit for Low-Power VLSI2004

    • Author(s)
      A.Mochizuki
    • Journal Title

      IEICE Transactions on Fundamentals. (to be published)

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-13558026
  • [Journal Article] Low-Power Motion-Vector Detection VLSI Processor Based on Pass-Gate Logic with Dynamic Supply-Voltage/Clock-Frequency Scaling2004

    • Author(s)
      A.Mochizuki
    • Journal Title

      IEICE Trans.on Electronics E87-C, 11

      Pages: 1876-1883

    • NAID

      110003214804

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] Low-Power Multiple-Valued Current-Mode Logic Using Substrate Bias Control2004

    • Author(s)
      A.Mochizuki
    • Journal Title

      IEICE Trans. on Electronics E87-C,4

      Pages: 582-588

    • NAID

      110003214894

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] Infra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding2004

    • Author(s)
      A.Mochizuki
    • Journal Title

      IEEE Int.Symposium on Multiple-Valued Logic 34

      Pages: 192-197

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding2004

    • Author(s)
      Akira Mochizuki
    • Journal Title

      Proc.IEEE International Symposium on Multiple-Valued Logic 34

      Pages: 192-197

    • Data Source
      KAKENHI-PROJECT-16700045
  • [Journal Article] 基盤バイアス制御に基づく低電力多値集積回路の構成2004

    • Author(s)
      望月 明
    • Journal Title

      電子情報通信学会2004年総合大会講演論文集 SC-11-11

    • Data Source
      KAKENHI-PROJECT-16700045
  • [Journal Article] Low-Power Pipelined VLSI System Using a Power-Supply-Controlled CMOS Pass-Gate Network and Its application2004

    • Author(s)
      A.Mochizuki
    • Journal Title

      ITC-CSCC 2004

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] Low-Power Pipelined VLSI System Using a Power-Supply-Controlled CMOS Pass-Gate Network and Its Application2004

    • Author(s)
      A.Mochizuki
    • Journal Title

      ITC-CSCC 2004 6C1L5-1/5-4

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] TMR-Based Logic-in-Memory Circuit for Low-Power VLSI2004

    • Author(s)
      A.Mochizuki
    • Journal Title

      IEICE Transactions on Fundamentals (to be published)

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-13558026
  • [Journal Article] Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding2004

    • Author(s)
      Akira Mochizuki
    • Journal Title

      Proc.34th IEEE International Symposium on Multiple-Valued Logic 34

      Pages: 192-197

    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding2004

    • Author(s)
      A.Mochizuki
    • Journal Title

      IEEE International Symposium on Multiple-Valued Logic 34

      Pages: 192-197

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] Dynamically Function-Programmable Bus Architecture for High-Throughput Intra-Chip Data Transfer2004

    • Author(s)
      A.Mochizuki
    • Journal Title

      IEICE Trans.on Electronics E87-C,11

      Pages: 1915-1922

    • NAID

      110003214810

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] 信号・しきい値多重化に基づく高性能電流モード多値回路の構成2004

    • Author(s)
      望月 明
    • Journal Title

      多値論理とその応用研究会技術研究報告 MVL-04,1

      Pages: 99-105

    • Data Source
      KAKENHI-PROJECT-16700045
  • [Journal Article] 差動対電流モード多値回路と高速・高信頼算術演算VLSIシステムへの応用2004

    • Author(s)
      望月 明
    • Journal Title

      信学技法 104,522

      Pages: 31-36

    • NAID

      110003318227

    • Data Source
      KAKENHI-PROJECT-16700045
  • [Journal Article] Low-Power Motion-Vector Detection VLSI Processor Based on Pass-Gate Logic With Dynamic Supply-Voltage/Clock-Frequency Scaling2004

    • Author(s)
      Akira Mochizuki
    • Journal Title

      IEICE Trans.on Electronics 87-C・11

      Pages: 1876-1883

    • NAID

      110003214804

    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] Low-Power Pipelined VLSI System Using a Power-Supply-Controlled CMOS Pass-Gate Network and Its application2004

    • Author(s)
      Akira Mochizuki
    • Journal Title

      ITC-CSCC 2004

    • Data Source
      KAKENHI-PROJECT-15500029
  • [Presentation] Active-Load Differential Comparator for Crosstalk-Noise Reduction2007

    • Author(s)
      A. Mochizuki, M. Miura, and T. Hanyu
    • Organizer
      37th IEEE International Symposium on Multiple-Valued Logic
    • Place of Presentation
      オスロ(ノルウェー)
    • Year and Date
      2007-05-16
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 超並列プロセッサ内多値データ転送方式2007

    • Author(s)
      白濱弘勝, 羽生貴弘, 中島雅美, 望月明, 有本和民
    • Place of Presentation
      神奈川
    • Year and Date
      2007-08-21
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Quaternary Processing Element for a Multi-Core VLSI processor2007

    • Author(s)
      H. Shirahama, T. Hanyu, M. Nakajima, A. Mochizuki, and K. Arimoto
    • Organizer
      4th International Workshop of Tohoku Univ. and Yeungnum Univ.
    • Place of Presentation
      松島
    • Year and Date
      2007-11-12
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Quaternary Processing Element for a Multi-Core VLSI processor2007

    • Author(s)
      H. Shirahama, T. Hanyu, M. Nakajima, A. Mochizuki and K. Arimoto
    • Place of Presentation
      Sendai, Japan
    • Year and Date
      2007-11-12
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor2007

    • Author(s)
      H. Shirahama, A. Mochizuki, T. Hanyu, M. Nakajima, K. Arimoto
    • Organizer
      37th IEEE International Symposium on Multiple-Valued Logic
    • Place of Presentation
      オスロ(ノルウェー)
    • Year and Date
      2007-05-16
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Active-Load Differential Comparator for Crosstalk-Noise Reduction2007

    • Author(s)
      A. Mochizuki, M. Miura and T. Hanyu
    • Place of Presentation
      Oslo, Norway
    • Year and Date
      2007-05-15
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor2007

    • Author(s)
      H. Shirahama, A. Mochizuki, T. Hanyu, M. Nakajima and K. Arimoto
    • Place of Presentation
      Oslo, Norway
    • Year and Date
      2007-05-15
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 超並列プロセッサ内多値データ転送方式2007

    • Author(s)
      白濱弘勝, 羽生貴弘, 中島雅美, 望月明, 有本和民
    • Organizer
      多値論理研究会
    • Place of Presentation
      湘南
    • Year and Date
      2007-08-22
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 2線差動論理に基づくノイズフリー多値集積回路2006

    • Author(s)
      三浦成友, 望月明, 羽生貴弘
    • Place of Presentation
      秋田
    • Year and Date
      2006-09-01
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Highly Reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic2006

    • Author(s)
      A. Mochizuki and T. Hanyu
    • Place of Presentation
      Singapore
    • Year and Date
      2006-05-18
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Design of a Microprocessor Data Path Using Four-Valued Differential-Pair Circuits2006

    • Author(s)
      A. Mochizuki, T. Kitamura, H. Shirahama and T. Hanyu
    • Place of Presentation
      Singapore
    • Year and Date
      2006-05-18
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Low-power Latch Based on Dynamic Differential Logic2006

    • Author(s)
      H. Shirahama, A. Mochizuki, T. Hanyu
    • Place of Presentation
      Gyeongju, Korea
    • Year and Date
      2006-11-17
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 差動ロジックに基づく高性能VLSIの展望2006

    • Author(s)
      望月明, 羽生貴弘
    • Place of Presentation
      宮城
    • Year and Date
      2006-08-23
    • Data Source
      KAKENHI-PROJECT-18300012
  • 1.  HANYU Takahiro (40192702)
    # of Collaborated Projects: 4 results
    # of Collaborated Products: 24 results
  • 2.  MATSUMOTO Atsushi (40455853)
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 0 results
  • 3.  NATSUI Masanori (10402661)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 4.  KAMEYAMA Michitaka (70124568)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 5.  KIMURA Hiromitsu (00361155)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results

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