KAMEYAMA Michitaka 亀山充隆

Researcher Number	70124568
Other IDs
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Affiliation (based on the past Project Information) *help	2011 – 2015: 東北大学, 情報科学研究科, 教授 2012: 東北大学, 大学院・情報科学研究科, 教授 2009 – 2010: Tohoku University, 大学院・情報科学研究科, 教授 2007: Tohoku University, Graduate School of Information Sciences, Professor 2006: 東北大学, 大学院情報科学研究科, 教授 … More 1993 – 2005: Tohoku University, Graduate school of Information Sciences, Professor, 大学院・情報科学研究科, 教授 2001 – 2002: 東北大学, 情報科学研究科, 教授 1998: Tohoku University, Graduate School of Information Science, Professor, 大学院・情報学研究科, 教授 1996: Tohoku University, Graduate School of Information Sciences, Professor, 大学院情報科学研究科, 教授 1995: 東北大学, 大学院・情報科学研究所, 教授 1994: 東北大学, 大学院情報科学研究科, 教授 1991 – 1992: PROFESSOR TOHOKU UNIVERSITY FACULTY OF ENGINEERING PROFESSOR, 工学部, 教授 1988 – 1990: 東北大学, 工学部, 助教授 1988: 東北大学, 工学部 1986: TOHOKU UNIVERSITY, FACULTY OF ENGINEERING, 工学部, 助教授 1985: 東北大学, 工, 助教授 Less
Review Section/Research Field	Principal Investigator Electron device/Electronic equipment / 計算機科学 / 計測・制御工学 / Computer system/Network / Control engineering / 計測・制御工学 / 情報工学 / Computer system Except Principal Investigator 計測・制御工学 / 計算機科学 / Electronic materials/Electric materials
Keywords	Principal Investigator 多値集積回路 / ロジックインメモリVLSI / 知能集積システム / ロジックインメモリアーキテクチャ / 電流源制御 / リコンフィギャラブルVLSI / ハイレベルシンセシス / Logic-In-Memory VLSI / 高並列演算回路 / 電流モード多値集積回路 … More / チップ内パケット転送 / LSI / Highly-Safe Intelligent Vehicle / 高安全知能自動車 / Dual-Rail Current-Mode Multiple-Valued Integrated Circuit / 2線式電流モード多値集積回路 / Logic-In-Memory Architecture / Allocation / Scheduling / High-Level Synthesis / Intelligent Integrated Systems for Real-World Applications / アロケーション / スケジューリング / リアルワールド応用知能集積システム / 並列構造VLSIプロセッサ / 算術演算回路 / 多値CAM / Reed-Muller Expansion / 低消費電力多値集積回路 / VLSIプロセッサ / ロボットエレクトロニクス / Intelligent Integrated Systems / 多値情報処理 / 空間的並列処理 / マイクロパケット転送 / Ｘネット / 差動対回路 / 多値電流モード集積回路 / 細粒度パイプライン / 多値ソースカップルドロジック / Neural network / Obstacle avoidance processor / Image recognition processor / Coordinate transformation processor / Parallel processing / Minimum delay time / Robot electronics / VLSI processor / データフローグラフ / VLSプロセッサ / 障害物回避プロセッサ / 画像確認プロセッサ / VISLプロセッサ / ニュ-ラルネットワ-ク / 障害物回避プソセッサ / 画像認識プロセッサ / 座標変換プロセッサ / 並列処理 / 演算遅れ時間最小 / pipelining / multiplier / digital signal processor / residue number system / ダイナミックシフトレジスタ / 乗算器 / ディジタル信号処理プロセッサ / 剰余数系 / Human Extraction / Vehicle Extraction / Road Extraction / Motion Estimation / Reconfigurable VLSI / High-level Synthesis / System-on-Chip / サンプリング周期 / システムレベル統合設計 / VLSIアーキテクチャ / ベイジアンネットワーク / 非同期アーキテクチャ / メモリアロケーション / ステレオビジョン / 人物抽出 / 車両抽出 / 道路抽出 / 軌道予測 / システムLSI / Low-Power VLSI Processor / ロジックインメモリーアーキテクチャ構造 / 低消費電力VLSI1プロセッサ / 低消費電力VLSIプロセッサ / Nonvolatile Logic-in-Mmemory / Ferro-Electric Device / Fine-Grain Pipelinign / Source-Coupled Logic / ステレオビジョンプロセッサ / パイプライン処理 / 多値VLSIプロセッサ / ソース結合形理論 / パストランジスタ理論 / ドミノ理論 / 電圧・電流ハイブリッドモード多値集積回路 / 不揮発ロジックインメモリ / 強誘電体デバイス / フルソースカップルドロジック / Partition Theory / Asynchronous Multiple-Valued VLSI / Highly-Parallel Arithmetic and Logic Circuit / Self Checking Circuit / 電力源制御 / 非同期多値演算回路 / 非同期式多値演算回路 / 分割理論 / Reed-Muller展開 / 非同期式多値VLSI / セルフチェッキング回路 / Interconnection Network / Spacially Parallel Structure / 3次元計測VLSIプロセッサ / パイプライン並列構造 / ステレオビジョンVLSIプロセッサ / 衝突チェックVLSIプロセッサ / 並列データ供給 / 演算遅れ時間最小化 / 相互結合回路網 / 空間並列構造 / ロジックインメモリアーキテクチャ構造 / One-Transistor CAM Cell / Multiple-Valued Memory / Multiple-Valued Threshold Operation / Magnitude Comparison / Multiple-Valued CAM / Highly Safe Vehicle / Floating-Gate MOS Transistor / Danger-Detection Rules / 非数値データ処理 / フローティングゲートMOSトランジスタ / 多値連想メモリ / 1トランジスタセル / 多値記憶 / 多値しきい演算 / 大小比較演算 / 高安全自動車 / フローティングゲートMOSFET / 危険検出ルール / Neural Network / Higher-Radix Arithmetic Circuits / Moving Picture Compression / Self-Timed Urtra-Highlv-Parallel Architecture / Functional Memory / Nueron MOS / Current-Mode Multiple-Valued Integrated Circuits / 超多値光コンピューティング / 多次元流れ型超並列処理 / 並列乗算器 / 実世界応用知能集積システム / 多波長光インタコネクション / 自己タイミング型超並列アーキテクチャ / フォールトトレラントニューラルネットワーク / 機能集積イメージセンサ / 自己タイミング超並列アーキテクチャ / ニューラルネットワーク / 高基数算術演算回路 / 動画像圧縮 / 自己タイミング長並列アーキテクチャ / 機能メモリ / ニューロンMOS / Low Power Multiple-Valued Integrated Circuit / Multiple-Valued Current-Mode Integrated Circuit / Redundant Coding / Critical-Path Minimization / Linear Digital Circuit / Highly Parallel Arithmetic and Logic Circuit / リ-ドマラ-展開 / 超高並列演算システム / クリティカルパス遅延最小化 / 多値冗長符号 / リ-ド・マラ-展開 / 線形演算回路 / System-On-Chip / Reconfigurable Parralel Processor / Linear Array Processor / Data-Dependcy Graph / VLSI Processors / Robot Electronics / Spatially Parallel Processing / 再構成可能プロセッサ / リニアアレー構造 / システムオンチップ / バス結合並列プロセッサ / 再構成可能並列プロセッサ / リニアアレープロセッサ / データ依存グラフ / Multiple-Valued Integrated Devices / Device-Model Based Electronics / Small Interconnection Delay / Small Critical-Delay Path / Ultra Fine Integrated Circuits / Linear Digital System / Highly Parallel Multiple-Valued Arithmetic and Logic Circuits / 空間的並列構造プロセッサ / 専用VLSIプロセッサ / 多値集積デバイス / デバイスモデルベーストエレクトロニクス / 微小配線遅延 / 微小クリティカルパス遅延 / 超微細集積回路 / 線形ディジタルシステム / 高並列多値演算回路 / Interconnection-free biomolecular computing / Ultra-many-valued logic network / Spacially parallel processing / Biochip / Biodevice model / Set logic operation / 無配線情報処理 / 並列選択性 / 多重化 / 完全並列処理 / 酵素センサ / 無配線バイオコンピューティング / 超多値論理回路網 / バイオチップ / バイオ素子モデル / 集合論理演算 / Residue Arithmetic VLSI / Current-Mode CMOS Integrated Circuit / Highly-Parallel Multiply Adder / Signed-Digit Arithmetic Circuit / Multiple-Valued Current-Mode Logic / Symmetric Residue Number System / 双方向電流モ-ドCMOS / 多値演算回路 / 高並列演算 / 剰余数演算回路 / VLSI / 剰余数演算VLSI / 電流モ-ドCMOS集積回路 / 高並列積和演算器 / SignedーDigit数演算回路 / 多値電流モ-ド論理 / 対称剰余数系 / 線形加算 / マルチプレクサロジック / 直接アロケーション / 多値Ｘネット / 多値差動対回路 / 細粒度リコンフィギャラブルVLSI / コンフィグレーションメモリサイズ減少 / 画像認識アルゴリズム / 画像認識 / 高安全システム / コンフィグレーションメモリサイズ / 階層構造ダイナミックリコンフィギャラブルVLSI / 危険要素検出 / コンフィグレーション／コントロールメモリ / ダイナミックリコンフィギャラブルVLSI / アルゴリズム選択 / VLSIプラットフォーム / リアルワールド応用 / 高安全知能システム / パワーゲーティング / 電流モード集積回路 / X ネット / コンフィグレーションメモリ / パケット転送制御 / リコンフィギャラブル VLSI / データ・制御信号重畳 / ビットシリアルアーキテクチャ / リコンフイギャラブルVLSI / ロジックインコントロール / 強誘電体ロジック / リアルタイムハイレベルシンセシス / 強誘電体不揮発ロジック / リアルタイム最適化 / 電流線形加算 / 2次元セルラアレー / 2線式ソースカップルドロジック / チップ内適応制御 / ダイナミック記憶 / 多値しきい論理 … More Except Principal Investigator 非数値データ処理 / フローティングゲートMOSトランジスタ / 知的情報処理 / パターンマッチングセル / 大小比較演算 / 超並列処理 / ロジックインメモリ構造 / しきい演算 / 多値連想メモリ / Intelligent Information Processing / Pattern Matching Cell / 4値CMOS集積回路 / 知能ロボット / 不揮発性ロジック / 記憶・演算一体化 / Quaternary Image Processor / Quaternary OM Cell / Quaternary CMOS Integrated Circuit / Multiple-Valued Digital Processing / Double Matching / Quaternary Logic System / Near-Neighbor Operation / Quaternary Complementary Pass Gate / ダブルパターンマッチング / 4値PM・セル / 画像処理プロセッサ / 4値PMセル / 多値情報処理 / ダブルパタ-ンマッチング / 多値論理演算 / 近傍論理演算 / 4値相補型パスゲ-ト / Multiple Iron Implant / Quaternary Integrated Circuit / AI / セル / パターンマッチング / 画像処理 / 多レベルイオン注入技術 / 4値集積回路 / 人工知能 / data-transfer bottleneck / operation merging / storage / resistor-circuit network / device modeling / fully parallel processing / ferroelectric capacitor / TMR device / multiple-valued logic-in-memory / 多値基本演算子 / マイクロ順序動作 / ゲートレベルパイプライン処理 / パイプライン乗算器 / 多値集積回路 / ゲートレベルパイプライン / FPGA / 強誘電体CAM / 相補的動作 / 非破壊読出し / デバイスモデル / 全加算器 / 強誘電体デバイス / データ転送ボトルネックフリー / 抵抗回路網 / デバイスモデリング / 超並列演算 / 強誘電体キャパシタ / TMR素子 / 多値ロジックインメモリ / Magnitude Comparison / Highly-Parallel Operation / Non-numeric Data Processing / Logic-in-Memory Architecture / Threshold Operation / Floating-Gate MOS Transistor / Multiple-Valued CAM / フローティングゲートMOSトランスジスタ / Intelligent information processing / Magnitude comparison / Fully parallel processing / Non-numeric data processing / Logic-in-memory VLSI architecture / Threshold operation / Floating-gate-MOS pass-transistor network / Multiple-valued content-addressable memory (CAM) / Ultimate Material and Process / Silicon Integrated Circuits / Intelligent electronic systems / 材料 / プロセス / デバイス / 回路 / 半導体プロセス / 集積回路 / シリコンテクノロジー / システム / マイクロエレクトロニクス / アーキテクチャ / 極限材料・プロセス / 知能情報処理 / シリコン集積回路 / 知的電子システム / 3-D Object Recognition / Clique Finding / Graph Matching / Object Recognition System / Inference VLSI Chip / Floating-Gate MOS-FET / 4-Valued CMOS Integrated Circuit / フロ-ティングゲ-トMOS-FET / パタ-ンマッチングセル / 超高速推論ハ-ドウェアエンジン / VLSIアレー / 3次元物体認識 / クリーク抽出 / グラフマッチング / 物体認識システム / 推論チップ / フローティングゲートMOS-FET / Dedicated VLSI Processor / Intelligent Robot / Redundant Robot / Free-Flying Robot / Flexible Robot / Dual Arm Robot / Telerobotics / Space Robot / 専用VLSIプロセッサ / 冗長自由度ロボット / 浮遊ロボット / フレキシブルロボット / 双腕ロボット / テレロボティクス / 宇宙ロボット / Multiple-Valued Super Chip / SD Multiplier / Modular Realization / SD Full-Adder / Multiple-Valued Bidirectional Current-Mode / SD Number System / 4進SD数加算器 / 高速算術演算用アレ- / セミカスタムVLSI / 設計容易性 / 指定配線数 / 多値モジュ-ルアレ- / 多値双方向電流モ-ド回路 / 多値SD数演算回路 / 知能ロボット用プロセッサ / ス-パ-チップ / 演算遅れ時間最小 / ロボットビジョン用VLSI / ロボット制御用VLSI / 4進SD数全加算器 / 多値双方向電流モ-ド / 多値ス-パ-チップ / 対称R進数 / SD数系 / マルチメディア応用 / Rambus / ISSCC / コミュニケーションVLSIプロセッサ / ニューパラダイムコンピユーティング / 高速データ転送技術 / 集積化 / シリコン / 知能エレクトロニクス Less

Development of a Data-Transfer-Bottleneck-Free Nonvolatile Logic-In-Memory Multiple-Valued VLSIPrincipal Investigator
- Principal Investigator
  
  Kameyama Michitaka
- Project Period (FY)
  2014 – 2015
- Research Category
  
  Grant-in-Aid for Challenging Exploratory Research
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Tohoku University
Design of a Universal VLSI Platform for Highly-Safe Intelligent Systems ApplicationsPrincipal Investigator
- Principal Investigator
  
  Kameyama Michitaka
- Project Period (FY)
  2013 – 2015
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system
- Research Institution
  Tohoku University
Multiple-Valued Reconfigurable VLSI Based on Adaptively Autonomous OperationPrincipal Investigator
- Principal Investigator
  
  KAMEYAMA Michitaka
- Project Period (FY)
  2011 – 2012
- Research Category
  
  Grant-in-Aid for Challenging Exploratory Research
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Tohoku University
ロジックインコントロール多値リコンフィギャラブルVLSIPrincipal Investigator
- Principal Investigator
  
  亀山充隆
- Project Period (FY)
  2009 – 2010
- Research Category
  
  Grant-in-Aid for Challenging Exploratory Research
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Tohoku University
自律適応制御を指向したプログラマブルロジックインメモリVLSIPrincipal Investigator
- Principal Investigator
  
  亀山充隆
- Project Period (FY)
  2006 – 2007
- Research Category
  
  Grant-in-Aid for Exploratory Research
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Tohoku University
Optimal VLSI Design for a Highly-Safe Intelligent Vehicle Based on a System Integration TheoryPrincipal Investigator
- Principal Investigator
  
  KAMEYAMA Michitaka
- Project Period (FY)
  2005 – 2007
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Tohoku University
超並列リコンフィギャラブル多値VLSIコンピューティングに関する研究Principal Investigator
- Principal Investigator
  
  亀山充隆
- Project Period (FY)
  2004 – 2005
- Research Category
  
  Grant-in-Aid for Exploratory Research
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Tohoku University
多値技術に基づく高速データ転送とそのマルチメディアVLSIプロセッサへの応用
- Principal Investigator
  
  HANYU Takahiro
- Project Period (FY)
  2002
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  計算機科学
- Research Institution
  Tohoku University
Implementation of a Transfer-Bottleneck-Free Multiple-Valued Logic-in-Memory VLSI and Its Application
- Principal Investigator
  
  HANYU Takahiro
- Project Period (FY)
  2001 – 2004
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  計算機科学
- Research Institution
  Tohoku University
Interconnection-Bottleneck-Free VLSI System Based on Dual-Rail Multiple-Valued Digital ComputingPrincipal Investigator
- Principal Investigator
  
  KAMEYAMA MICHITAKA
- Project Period (FY)
  2000 – 2002
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  計算機科学
- Research Institution
  Tohoku University
Development of VLSI Processor Chip Family for Highly-Safe Intelligent Vehicles Based on Optimal Design MythologiesPrincipal Investigator
- Principal Investigator
  
  KAMEYAMA Michitaka
- Project Period (FY)
  2000 – 2002
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Control engineering
- Research Institution
  Tohoku University
Ultimate Integration of Intelligence on Silicon Electronic Systems
- Principal Investigator
  
  OHMI Tadahiro
- Project Period (FY)
  1999
- Research Category
  
  Grant-in-Aid for Scientific Research on Priority Areas (A)
- Research Institution
  Tohoku University
MULTIPLE-VALUED PROCESSOR FOR INTELLIGENT INTEGRATED SYSTEM
- Principal Investigator
  
  HANYU Takahiro
- Project Period (FY)
  1997 – 1998
- Research Category
  
  Grant-in-Aid for international Scientific Research
- Research Field
  
  計算機科学
- Research Institution
  TOHOKU UNIVERSITY
High-Level Synthesis of High-Performance VLSI Processors for Intelligent Integrated SystemPrincipal Investigator
- Principal Investigator
  
  KAMEYAMA Michitaka
- Project Period (FY)
  1997 – 1999
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  計測・制御工学
- Research Institution
  TOHOKU UNIVERSITY
Development of a Chip Family for Ultra-Highly-Parallel Multiple-Valued Integrated Circuits and Its ApplicationsPrincipal Investigator
- Principal Investigator
  
  KAMEYAMA Michitaka
- Project Period (FY)
  1997 – 1999
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  計算機科学
- Research Institution
  TOHOKU UNIVERSITY
Implementation of a One-Transistor Multiple-Valued Content-Addressalbe Memory and Its Application
- Principal Investigator
  
  HANYU Takahiro
- Project Period (FY)
  1997 – 2000
- Research Category
  
  Grant-in-Aid for Scientific Research (B).
- Research Field
  
  計算機科学
- Research Institution
  Tohoku Univesity
Ultra-Parallel and Ultra-High-Speed Architecture for Ultimate IntegrationPrincipal Investigator
- Principal Investigator
  
  KAMEYAMA Michitaka
- Project Period (FY)
  1995 – 1998
- Research Category
  
  Grant-in-Aid for Scientific Research on Priority Areas
- Research Institution
  Tohoku University
Study on Multiple-Valued VLSI Processors for a Highly Safe Intelligent VehiclePrincipal Investigator
- Principal Investigator
  
  KAMEYAMA Michitaka
- Project Period (FY)
  1995 – 1996
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  計算機科学
- Research Institution
  Tohoku University
極限集積化シリコン知能エレクトロニクス
- Principal Investigator
  
  OHMI Tadahiro
- Project Period (FY)
  1994
- Research Category
  
  Grant-in-Aid for Co-operative Research (B)
- Research Field
  
  Electronic materials/Electric materials
- Research Institution
  Tohoku University
Ultra-Highly-Parallel Arithmetic and Logic Circuits and Their Multiple-Valued IntegrationPrincipal Investigator
- Principal Investigator
  
  KAMEYAMA Michitaka
- Project Period (FY)
  1994 – 1996
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  計算機科学
- Research Institution
  Tohoku University, Graduate School of Information Sciences
Study on Post-Binary ULSI SstemsPrincipal Investigator
- Principal Investigator
  
  KAMEYAMA Michitaka
- Project Period (FY)
  1992 – 1993
- Research Category
  
  Grant-in-Aid for international Scientific Research
- Research Institution
  Tohoku University, Graduate School of Information Sciences
Development of VLSI Processors for Robot Control with Ultra-High Performance in the Arithmetic DelayPrincipal Investigator
- Principal Investigator
  
  KAMEYAMA Michitaka
- Project Period (FY)
  1992 – 1994
- Research Category
  
  Grant-in-Aid for Developmental Scientific Research (B)
- Research Field
  
  情報工学
- Research Institution
  Tohoku University, Graduate School of Information Sciences
IMPLEMENTATION OF ULTRA-HIGH-SPEED INFERENCE HARDWARE ENGINE BASED ON 4-VALUED CMOS INTEGRATED CIRCUITS AND ITS APPLICATION
- Principal Investigator
  
  HIGUCHI Tatsuo
- Project Period (FY)
  1991 – 1992
- Research Category
  
  Grant-in-Aid for Developmental Scientific Research (B)
- Research Field
  
  計測・制御工学
- Research Institution
  TOHOKU UNIVERSITY
Ultra-Many-Valued, Highly Parallel Computing System for Biochip ImplementationPrincipal Investigator
- Principal Investigator
  
  KAMEYAMA Michitaka
- Project Period (FY)
  1991 – 1992
- Research Category
  
  Grant-in-Aid for General Scientific Research (C)
- Research Field
  
  計測・制御工学
- Research Institution
  Tohoku University
Study on Dual Arm Intelligent Robot for Space Application
- Principal Investigator
  
  UCHIYAMA Masaru, 内山勝
- Project Period (FY)
  1990
- Research Category
  
  Grant-in-Aid for international Scientific Research
- Research Institution
  Tohoku University
BASIC STUDY ON HIGH-PERFORMANCE MULTIPLE-VALUED SUPER CHIP FOR INTELLIGENT ROBOTS
- Principal Investigator
  
  HIGUCHI Tatsuo
- Project Period (FY)
  1989 – 1991
- Research Category
  
  Grant-in-Aid for General Scientific Research (B)
- Research Field
  
  計測・制御工学
- Research Institution
  TOHOKU UNIVERSITY
Implementation of an Ultra-Higyly Parallel Residue Arithemtic Integrated Circuit Based on Multiple-Vlaued Logic and its EvaluationPrincipal Investigator
- Principal Investigator
  
  KAMEYAMA Michitaka
- Project Period (FY)
  1989 – 1990
- Research Category
  
  Grant-in-Aid for Developmental Scientific Research (B).
- Research Field
  
  計測・制御工学
- Research Institution
  Tohoku University
VLSI-Based Robot Electronics SystemPrincipal Investigator
- Principal Investigator
  
  KAMEYAMA Michitaka
- Project Period (FY)
  1988 – 1989
- Research Category
  
  Grant-in-Aid for General Scientific Research (C)
- Research Field
  
  計測・制御工学
- Research Institution
  Tohoku University
IMPLEMENTATION OF QUATERNARY CMOS INTEGRATED CIRCUIT FOR DOUBLE MATCHING ALGORITHM AND ITS APPLICATION TO MULTIPLE-VALUED DIGITAL PROCESSING SYSTEM
- Principal Investigator
  
  HIGUCHI Tatsuo
- Project Period (FY)
  1988 – 1989
- Research Category
  
  Grant-in-Aid for Developmental Scientific Research
- Research Field
  
  計測・制御工学
- Research Institution
  TOHOKU UNIVERSITY
IMPLEMENTATION OF QUATERNARY INTEGRATED CIRCUITS FOR AI-ORIENTED PATTERN MATCHING CELLS AND THEIR APPLICATION
- Principal Investigator
  
  HIGUCHI TATSUO
- Project Period (FY)
  1985 – 1986
- Research Category
  
  Grant-in-Aid for Developmental Scientific Research
- Research Field
  
  計測・制御工学
- Research Institution
  TOHOKU UNIVERSITY
LSI-Oriented Digital Signal Processing System Based on Residue Arithemtic Circuits and Its Comprehensive EvaluationPrincipal Investigator
- Principal Investigator
  
  KAMEYAMA Michitaka
- Project Period (FY)
  1984 – 1985
- Research Category
  
  Grant-in-Aid for Developmental Scientific Research
- Research Field
  
  計測・制御工学
- Research Institution
  Tohoku University

All 2016 2015 2014 2013 2012 2011 2010 2009 2007 2006 2005 2004 Other

All Journal Article Presentation

[Journal Article] Algorithm Selection Platform in Real-World Intelligent Systems2015
- Author(s)
  Martin Lukac, Kamila Abdiyeva, Yoshichika Fujioka, Michitaka Kameyama
- Journal Title
  
  28th InterncationConference on Computer Applications in Industry and Engineering
  
  Volume: - Pages: 227-234
- Peer Reviewed / Acknowledgement Compliant / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280011
[Journal Article] Evaluation of Algorithm Selection Approach for Semantic Segmentation Based on High-Level Information Feedback2015
- Author(s)
  Martin Lukac, Kamila Abdiyeva, Michitaka Kameyama
- Journal Title
  
  International Conference on Information and Digital Technologies
  
  Volume: - Pages: 212-218
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280011
[Journal Article] Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators2015
- Author(s)
  Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama and Michitaka Kameyama
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E98.A Issue: 12 Pages: 2658-2669
- DOI
  10.1587/transfun.E98.A.2658
- NAID
  130005111969
- ISSN
  0916-8508, 1745-1337
- Language
  English
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-15J04973, KAKENHI-PROJECT-24300013, KAKENHI-PROJECT-25280011
[Journal Article] Novel VLSI Architectures for Real-World Intelligent Systems2015
- Author(s)
  Michitaka Kameyama
- Journal Title
  
  IEEE 45th International Symposium on Multiple-Valued Logic
  
  Volume: ー Pages: 132-132
- DOI
  10.1109/ismvl.2015.39
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-26630145
[Journal Article] Bayesian-Network-Based Algorithm Selection with High Level Representation Feedback for Real-World Intelligent Systems2015
- Author(s)
  Lukac M., Kameyama M.
- Journal Title
  
  IT in Industry
  
  Volume: Vol.3, Issue.1 Pages: 10-15
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-25280011
[Journal Article] Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path2015
- Author(s)
  Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama
- Journal Title
  
  IEEE Transactions on Very Large Scale Integration Systems
  
  Volume: Vol.23, No．4 Issue: 4 Pages: 619-630
- DOI
  10.1109/tvlsi.2014.2314685
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-25280011
[Journal Article] Symbolic Segmentation Using Algorithm Selection and Semantic Feedback2015
- Author(s)
  Martin Lukac, Kamila Abdiyeva, Michitaka Kameyama
- Journal Title
  
  Scene Understanding Workshop 2015
  
  Volume: -
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280011
[Journal Article] Automatic Algorithm Selection for Real-World Intelligent Systems Platform2014
- Author(s)
  Martin Lukac, Michitaka Kameyama and Yoshichika Fujioka
- Journal Title
  
  Proceedings of the 23rd International Workshop on Post-Binary ULSI Systems
  
  Volume: - Pages: 7-14
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-25280011
[Journal Article] Bayesian-Network-Based Algorithm Selection with High Level Representation Feedback for Real-World Intelligent Systems2014
- Author(s)
  Martin Lukac and Michitaka Kameyama
- Journal Title
  
  The 9th International Conference on Information Technology and Applications (ICITA 2014)
  
  Volume: -
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-25280011
[Journal Article] Implementation of Voltage-Mode/Current-Mode Hybrid Circuits for a Low-Power Fine-Grain Reconfigurable VLSI2014
- Author(s)
  Xu Bai and Michitaka Kameyama
- Journal Title
  
  IEICE Trans. Electron.
  
  Volume: E97.C Issue: 10 Pages: 1028-1035
- DOI
  10.1587/transele.E97.C.1028
- NAID
  130004696706
- ISSN
  0916-8524, 1745-1353
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-26630145
[Journal Article] An Asynchronous High-Performance FPGA Based on LEDR/Four-Phase-Dual-Rail Hybrid Architecture2014
- Author(s)
  Yoshiya Komatsu, Masanori Hariyama and Michitaka Kameyama
- Journal Title
  
  Proceedings of the 5th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies
  
  Volume: - Pages: 111-114
- NAID
  110009925727
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-25280011
[Journal Article] Multiple-Valued Fine-Grain Reconfigurable VLSI Using a Global Tree Local X-Net Network2014
- Author(s)
  Xu Bai and Michitaka Kameyama
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E97.D Issue: 9 Pages: 2278-2285
- DOI
  10.1587/transinf.2013LOP0006
- NAID
  130004685460
- ISSN
  0916-8532, 1745-1361
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-26630145
[Journal Article] Design of a Logic-in-Memory Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme2014
- Author(s)
  Shintaro Harada, Xu Bai, Michitaka Kameyama and Yoshichika Fujioka
- Journal Title
  
  IEEE 44th International Symposium on Multiple-Valued Logic
  
  Volume: - Pages: 214-219
- DOI
  10.1109/ismvl.2014.45
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-26630145
[Journal Article] Architecture of an Asynchronous FPGA for Handshake-Component-Based Design2013
- Author(s)
  Yoshiya Komatsu , Masanori Hariyama, Michitaka Kameyama
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E96.D Issue: 8 Pages: 1632-1644
- DOI
  10.1587/transinf.E96.D.1632
- NAID
  130003370945
- ISSN
  0916-8532, 1745-1361
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-13J05513, KAKENHI-PROJECT-25280011
[Journal Article] VLSI Platform for Real-World Intelligent Integrated Systems Based on Algorithm Selection2013
- Author(s)
  Martin Lukac, Michitaka Kameyama1 and Yoshichika Fujiokam
- Journal Title
  
  IADIS Theory and Practice in Modern Computing
  
  Volume: - Pages: 27-34
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-25280011
[Journal Article] A Low-Power FPGA Based on Self-Adaptive Multi-Voltage Control2013
- Author(s)
  Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama
- Journal Title
  
  Proc. International SoC Design Conference
  
  Volume: - Pages: 166-169
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-25280011
[Journal Article] Bayesian Network for Algorithm Selection: Real-World Hierarchy for Nodes Reduction2013
- Author(s)
  Lukac M. and Kameyama M.
- Journal Title
  
  International Conference on Awareness Science and Technology
  
  Volume: - Pages: 69-75
- DOI
  10.1109/icawst.2013.6765411
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-25280011
[Journal Article] A Bit-Serial Reconfigurable VLSI Based on a Multiple-Valued X-Net Data Transfer Scheme2013
- Author(s)
  Xu Bai, Michitaka Kameyama
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E96.D Issue: 7 Pages: 1449-1456
- DOI
  10.1587/transinf.E96.D.1449
- NAID
  130003370921
- ISSN
  0916-8532, 1745-1361
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-25280011
[Journal Article] VLSI platform for Real-World Intelligent Integrated Systems based on Algorithm Selection2013
- Author(s)
  Martin Lukac, Michitaka Kameyama and Yoshichika Fujioka
- Journal Title
  
  IADIS International Journal on Computer Science and Information Systems
  
  Volume: Vol.8, No.2 Pages: 72-90
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-25280011
[Journal Article] An Area-Efficient Multiple-Valued Reconfigurable VLSI Architecture Using an X-Net2013
- Author(s)
  Xu Bai, Michitaka Kameyama
- Journal Title
  
  Proceedings of the 43th IEEE International Symposium on Multiple-Valued Logic
  
  Volume: - Pages: 272-277
- DOI
  10.1109/ismvl.2013.13
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-25280011
[Journal Article] An Area-Efficient Asynchronous FPGA Architecture for Handshake-Component-Based Design2013
- Author(s)
  Yoshiya Komatsu, Masanori Hariyama and Michitaka Kameyama
- Journal Title
  
  Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms
  
  Volume: - Pages: 15-18
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-25280011
[Journal Article] A Digit-Serial Reconfigurable VLSI Based on Quaternary Inter-Cell Data Transfer Scheme2013
- Author(s)
  Xu Bai, Nobuaki Okada and Michitaka Kameyama
- Journal Title
  
  Journal of Multiple-Valued Logic and Soft Computing
  
  Volume: Vol.20 Pages: 1-18
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23656230
[Journal Article] Current-Source-Sharing Differential-Pair Circuits for a Low-Power Fine-Grain Reconfigurable VLSI Architecture2012
- Author(s)
  Xu Bai and Michitaka Kameyama
- Journal Title
  
  Proceedings of 2012 IEEE International Symposium on Multiple-Valued Logic
  
  Pages: 208-213
- DOI
  10.1109/ismvl.2012.13
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23656230
[Journal Article] Configuration Memory Size Reduction of a Dynamically Reconfigurable Processor Based on a Register-Transfer-Level Packet Data Transfer Scheme2012
- Author(s)
  Yoshichika Fujioka and Michitaka Kameyama
- Journal Title
  
  Proceedings of 2012International SoC Design Conference
  
  Pages: 235-238
- DOI
  10.1109/isocc.2012.6407083
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23656230
[Journal Article] Unified Current-Source Control for Low-Power Current-Mode-Logic Bit-Serial Circuits2012
- Author(s)
  Shogo Kisara and Michitaka Kameyama
- Journal Title
  
  Proceedings of 2012 IEEE InternationalSymposium on Multiple-Valued Logic
  
  Pages: 104-109
- DOI
  10.1109/ismvl.2012.55
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23656230
[Journal Article] A Switch Block for Multi-Context FPGAs Based on Floating-Gate-MOS Functional Pass-Gates Using Multiple/Binary Valued HybridSignals2011
- Author(s)
  Shota Ishihara, Noriaki Idobata, Yoshihiro Nakatani, Masanori Hariyama and Michitaka Kameyama
- Journal Title
  
  Journal of Multiple-Valued Logic and Soft Computing
  
  Volume: Vol.17 Pages: 553-580
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23656230
[Journal Article] Information-Preserving Logic Based on Logic Reversibility to Reduce the Memory Data Transfer and Heat Dissipation2011
- Author(s)
  M.Lukac, B.Shuai, M. Kameyama and D.M.Miller
- Journal Title
  
  Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic
  
  Pages: 131-138
- DOI
  10.1109/ismvl.2011.43
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23656230
[Journal Article] A Switch Block for Multi-Context FPGAs Based on Floating-Gate-MOS Functional Pass-Gates Using Multiple/Binary Valued Hybrid Signals2011
- Author(s)
  Shota Ishihara, Noriaki Idobata, Yoshihiro Nakatani, Masanori Hariyama, and Michitaka Kameyama
- Journal Title
  
  Journal of Multiple-Valued Logic and Soft Computing
  
  Volume: Vol.17 Pages: 553-580
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23656230
[Journal Article] Low-Power Multiple-Valued Reconfigurable VLSI Based on Superposition of Bit-Serial Data and Current-Source Control Signals2010
- Author(s)
  Akitaka Ishikawa, Nobuaki Okada, Michitaka Kameyama
- Journal Title
  
  Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic
  
  Volume: (CD-ROM) Pages: 179-184
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21656088
[Journal Article] Logic-In-Control-Architecture Based Reconfigurable VLSI Using Multiple-Valued Differential-Pair Circuits2010
- Author(s)
  Nobuaki Okada, Michitaka Kameyama
- Journal Title
  
  IEICE Transactions on Information and Systems
  
  Volume: Vol.E93-D No.8 Pages: 2126-2133
- NAID
  10027364623
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21656088
[Journal Article] Multiple-Valued Reconfigurable VLSI Processor Based on Superposition of Data and Control Signals2009
- Author(s)
  Nobuaki Okada, Michitaka Kameyama
- Journal Title
  
  39th IEEE International Symposium on Multiple-Valued Logic CD-ROM
  
  Pages: 54-59
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21656088
[Journal Article] Design of a Fine-Grain Reconfigurable VLSI Based on Logic-In-Control Architecture2009
- Author(s)
  Nobuaki Okada, Michitaka Kameyama
- Journal Title
  
  2009 International SoC Design Conference CD-ROM
  
  Pages: 278-281
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21656088
[Journal Article] Design of a Multi-Context FPVLSI based on an AsynchronousBit-Serial Architecture2007
- Author(s)
  Waidyasooriya Hasitha Muthumala, Masanori Hariyama, and Michitaka Kameyama
- Journal Title
  
  Sixth IEEE Dallas Circuits and SystemsWorkshop
  
  Pages: 59-62
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation2007
- Author(s)
  Tasuku ITO and Michitaka KAMEYAMA
- Journal Title
  
  IEEE International Symposium on Multiple-Valued Logic (CD-ROM)
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18656101
[Journal Article] セミオートノマスパケットルーティングに基づく高並列VLSIプロセッサの構成2007
- Author(s)
  藤岡与周, 苫米地宣裕, 亀山充隆
- Journal Title
  
  電気関係学会東北支部連合大会 2E17
  
  Pages: 191-191
- NAID
  130005444439
- Data Source
  KAKENHI-PROJECT-18656101
[Journal Article] Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation2007
- Author(s)
  Tasuku ITO and Michitaka KAMEYAMA
- Journal Title
  
  Journal of Multiple-Valued Logic and Soft Computing Vol.13
  
  Pages: 553-567
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18656101
[Journal Article] 細粒度アーキテクチャに基づくフィールドプログラマブルVLSIの開発2007
- Author(s)
  張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会エレクトロニクスソサイエティ大会 C-12-11
  
  Pages: 66-66
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 超高速ステレオビジョンVLSIプロセッサの設計2007
- Author(s)
  張山昌論, 横山直人, 吉田恒, 亀山充隆
- Journal Title
  
  第13回画像センシングシンポジウム予稿集
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] ウィンドウ演算のための最適スケジューリング・メモリアロケーション2007
- Author(s)
  小林康浩, 張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会論文誌 Vo1. J90-D, No.5
  
  Pages: 1178-1193
- NAID
  110007380712
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 演算器レベル・パケット転送方式に基づく高並列VLSIプロセッサの構成2007
- Author(s)
  藤岡与周, 苫米地宣裕, 亀山充隆
- Journal Title
  
  電子情報通信学会技術報告 ICD2007-34
  
  Pages: 103-108
- NAID
  110006291423
- Data Source
  KAKENHI-PROJECT-18656101
[Journal Article] ユニバーサルな知能集積システムの構築を目指して2007
- Author(s)
  亀山充隆
- Journal Title
  
  多値論理研究ノート Vo1. 30, No.10
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 形状特徴を用いた人物抽出アルゴリズムとそのVLSIアーキテクチャ2007
- Author(s)
  橋本翔太, 佐々木明夫, 張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会信学技報 Vol.107,No.382,ICD2007-13
  
  Pages: 77-82
- NAID
  110006546968
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] ウィンドウ演算のための最適スケジューリング・メモリアロケーション2007
- Author(s)
  小林康浩, 張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会論文誌 Vol.J90-D,No.5
  
  Pages: 1178-1193
- NAID
  110007380712
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] A Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture2007
- Author(s)
  Masanori Hariyama, Shota Ishihara, Chang Chia Wei and Michitaka Kameyama
- Journal Title
  
  IEEE Asian Solid-State Circuits Conference
  
  Pages: 380-383
- NAID
  110006546969
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 相互結合網簡単化を考慮した遺伝的アルゴリズムに基づく電源・しきい値電圧割当2007
- Author(s)
  ウィシディスーリヤハシタムトゥマラ, 張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会技術報告 ICD2007-31
  
  Pages: 85-90
- NAID
  110006291420
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] ユニバーサルな知能集積システムの構築を目指して2007
- Author(s)
  亀山充隆
- Journal Title
  
  多値論理研究ノート Vol.30,NO.10
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Design of a Multi-Context FPVLSI based on an Asynchronous Bit-Serial Architecture2007
- Author(s)
  Waidyasooriya Hasitha Muthumala, Masanori Hariyama, and Michitaka Kameyama
- Journal Title
  
  Sixth IEEE Dallas Circuits and Systems Workshop
  
  Pages: 59-62
- NAID
  120001182116
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 非同期ビットシリアルアーキテクチャに基づくフィールドプログラマブルVLSIの構成2007
- Author(s)
  石原翔太, 張山昌論, 亀山充隆
- Journal Title
  
  電気関係学会東北支部連合大会 2E18
  
  Pages: 192-192
- NAID
  130005444444
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits2007
- Author(s)
  Nobuaki Okada, and Michitaka Kameyama
- Journal Title
  
  Journal of Multiple-Valued Logic and Soft Computing Vol.13, No.4-6
  
  Pages: 619-631
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18656101
[Journal Article] クリティカルパス連鎖演算ノードのグループ化に基づくレジスタ転送レベル実時間最適化2007
- Author(s)
  工藤隆男, 亀山充隆
- Journal Title
  
  電気関係学会東北支部連合大会 2E16
  
  Pages: 190-190
- NAID
  130005444438
- Data Source
  KAKENHI-PROJECT-18656101
[Journal Article] 相互結合網簡単化を考慮した遺伝的アルゴリズムに基づく電源・しきい値電圧割当2007
- Author(s)
  ウィシディスーリヤハシタムトゥマラ, 張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会技術報告 ICD2007-31
  
  Pages: 85-90
- NAID
  110006291420
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] データ圧縮に基づく画像処理VLSIアーキテクチャとその応用2007
- Author(s)
  吉田恒, 小林康浩, 張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会技術研究報告 ICD2007-100
  
  Pages: 11-14
- NAID
  110006453357
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 3次元情報を用いた車両検出アルゴリズムとそのVLSIアーキテクチャ2007
- Author(s)
  山下健策, 佐々木明夫, 張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会技術研究報告 ICD2007-99
  
  Pages: 5-9
- NAID
  110006453356
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Design of a Multi-Context FPVLSI based on an AsynchronousBit-Serial Architecture2007
- Author(s)
  Waidyasooriya Hasitha Muthumala, Masanori Hariyama, and Michitaka Kameyama
- Journal Title
  
  Sixth IEEE Dallas Circuits and Systems Workshop
  
  Pages: 59-62
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 操作系列特徴に基づく情報家電ユーザ支援用確率推論システム2007
- Author(s)
  千頭和周平, 亀山充隆
- Journal Title
  
  電気関係学会東北支部連合大会 1E08
  
  Pages: 165-165
- NAID
  130005444408
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits2007
- Author(s)
  Nobuaki Okada, and Michitaka Kameyama
- Journal Title
  
  IEEE International Symposium on Multiple-Valued Logic (CDROM)
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18656101
[Journal Article] 差動対回路を用いた全加算器ベース演算セルを構成要素とする多値リコンフィギャラブルVLSI2007
- Author(s)
  岡田信彬, 亀山充隆
- Journal Title
  
  多値技報 Vol.MVL-08, No.1
  
  Pages: 10-15
- Data Source
  KAKENHI-PROJECT-18656101
[Journal Article] 形状特徴を用いた人物抽出アルゴリズムとそのVLSIアーキテクチャ2007
- Author(s)
  橋本翔太, 佐々木明夫, 張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会信学技報 Vol.107, No.38 2,ICD-2007-133
  
  Pages: 77-82
- NAID
  110006546968
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 電圧・電流制御に基づく低電力化を指向した多値リコンフィギャラブルVLSI2006
- Author(s)
  岡田信彬, ハアクモハマッドムニルル, 亀山充隆
- Journal Title
  
  電子情報通信学会技術報告 ICD2006-50
  
  Pages: 57-61
- NAID
  110004748906
- Data Source
  KAKENHI-PROJECT-18656101
[Journal Article] Prospects of Intelligent Integrated Systems for Real-World Applications2006
- Author(s)
  Michitaka Kameyama
- Journal Title
  
  IEEE International Conference on Computers and Devices for Communication, CD-ROM (CD-ROM)
- NAID
  10007386690
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Architecture of a Multi-Context FPGA Using a hybrid Multiple-Valued/Binary Context Switching Signal2006
- Author(s)
  Yoshihiro NAKATANI, Masanori HARIYAMA, Michitaka KAMEYAMA
- Journal Title
  
  Reconfigurable Architectures Workshop (CDROM)
- NAID
  120001182127
- Data Source
  KAKENHI-PROJECT-18656101
[Journal Article] Optimal Periodical Memory Allocation for Logic-in-Memory Imag Processors2006
- Author(s)
  Masanori Hariyama, Michitaka Kameyama, and Yasuhiro Kobayashi
- Journal Title
  
  IEEE Computer Society Anual Symposium on VLSI
  
  Pages: 193-196
- NAID
  120001182132
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] チッフ内細粒度パケット転送に基づく高並VLSIフロセッサの構成2006
- Author(s)
  藤岡与周, 苫米地宣弘, 亀山充隆
- Journal Title
  
  電子情報通信字会エレクトロニクスソサイエティ大会 C-12-3
  
  Pages: 64-64
- Data Source
  KAKENHI-PROJECT-18656101
[Journal Article] Prospects of Intelligent Integrated Systems for Real-World Applications2006
- Author(s)
  Michitaka Kameyama
- Journal Title
  
  IEEE International Conference on Computers and Devices for Communication CD-ROM
- NAID
  10007386690
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Bayesian-Networks-Based Motion Estimation for a Highly-Safe Intelligent Vehicle2006
- Author(s)
  Nguyen Van Dan, Michitaka Kameyama
- Journal Title
  
  SICE-ICASE International Joint Conference
  
  Pages: 6023-6026
- NAID
  120001182138
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued Binary Context Switching Signals2006
- Author(s)
  Yoshihiro NAKATANI, Masanori HARIYAMA, Michitaka KAMEYAMA
- Journal Title
  
  International Symposium on Multiple-values Logic (CDROM)
- NAID
  120001182130
- Data Source
  KAKENHI-PROJECT-18656101
[Journal Article] Processor Architecture for Road Extraction Based on Projective Transformation2006
- Author(s)
  Sunggae Lee, Masanori Hariyama, Michitaka Kameyama
- Journal Title
  
  SICE-ICCAS
  
  Pages: 1446-1450
- NAID
  110004748907
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Optimal Periodical Memory Allocation for Logic-in-memory imag Processors2006
- Author(s)
  Masanori Hariyama, Michitaka kameyama, and yasuhiro Kobayashi
- Journal Title
  
  IEEE Computer Society Anual Symposium on VLSI
  
  Pages: 193-198
- NAID
  120001182132
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Processor Architecture for Road Extraction Based on Projective Transformation2006
- Author(s)
  Sunggae Lee, masanori Hariyama and Michitaka Kameyama
- Journal Title
  
  SICE-ICCAS
  
  Pages: 1446-1450
- NAID
  110004748907
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Dynamically Reconfigurable Gata Array Based on Fine-Grained Switch Elements and Its CAD Environment2006
- Author(s)
  Masanori hariyama, Waidyasoority Hasitha muthumala, and Michitaka Kameyama
- Journal Title
  
  Proc. Asian Solid-State Circuits conference
  
  Pages: 155-158
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Bayesian-Networks-Based Motion Estimation for a Highly-Safe Intelligent Vehicle2006
- Author(s)
  Nguyen Van Dan and Michitaka Kameyama
- Journal Title
  
  SICE-ICASE International Joint Conference
  
  Pages: 6023-6026
- NAID
  120001182138
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 1000frame/sec Stereo Matching VLSI Processor with Adaptive Window-Size Control2006
- Author(s)
  Masanori Hariyama, Naoto Yokoyama, Michitaka Kameyama
- Journal Title
  
  Proc. Asian Solid-State Circuits Conference
  
  Pages: 123-126
- NAID
  120001182113
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Functional-Unit-Level Packet Data Transfer Scheme for a Highly Parallel VLSI Processor2006
- Author(s)
  Yoshichika Fujioka, Nobuhiro Tomabechi, Michitaka Kameyama
- Journal Title
  
  IEEE International Conference on Computers and Devices for Communication (CD-ROM)
- Data Source
  KAKENHI-PROJECT-18656101
[Journal Article] A Multi-Context FPGA Using A Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment2006
- Author(s)
  Masanori Hariyama, Michitaka Kameyama
- Journal Title
  
  IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
  
  Pages: 1805-1808
- NAID
  120001182110
- Data Source
  KAKENHI-PROJECT-18656101
[Journal Article] Prospects of Intelligent Integrated Systems for Real-World Applications2006
- Author(s)
  Michitaka Kameyama
- Journal Title
  
  IEEE International Conference on Computers and Devices for Communication (CD-ROM)
- NAID
  10007386690
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 高安全自動車道路抽出のための動的再構成可能アーキテクチャ2006
- Author(s)
  李承啓, 張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会技術報告 ICD2006-51
  
  Pages: 63-67
- NAID
  110004748907
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 強誘電体機能パスケートを用いたマルチコンクストFPGAのアーキテクチャ2006
- Author(s)
  中谷好博, 張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会技術報告 ICD2006-143
  
  Pages: 1-6
- Data Source
  KAKENHI-PROJECT-18656101
[Journal Article] 画像処理プロセッサのための最適メモリアロケーション2006
- Author(s)
  張山昌論, 小林康浩, 亀山充隆
- Journal Title
  
  電子情報通信学会技術報告 ICD2006-57
  
  Pages: 95-100
- NAID
  110004748913
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification2006
- Author(s)
  Masanori HARIYAMA, Shigeo YAMADERA, and Michitaka KAMEYAMA
- Journal Title
  
  IEICE Trans. Electron. Vol. E89-C, No. 11
  
  Pages: 1551-1558
- NAID
  110007538691
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 1000frame/sec Stereo Mateching VLSI Processor with Adaptive Window-Size Control2006
- Author(s)
  Masanori Hariyama, Nato Yokoyama and Michitaka Kameyama
- Journal Title
  
  Proc. Asian Solid-State Circuits Conference
  
  Pages: 123-126
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Bayesian-Networks-Based Motion Estimation for a Highly-Safe Intelligent Vehicle2006
- Author(s)
  Nguyen Van Dan and Michitaka Kameyama
- Journal Title
  
  SICE-ICASE international Joint Conference
  
  Pages: 6023-6026
- NAID
  120001182138
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Advanced VLSI Architecture for intelligent Integrated Systems2006
- Author(s)
  Michitaka Kameyama
- Journal Title
  
  Proceedings AWAD 2006
  
  Pages: 1-6
- NAID
  110004813184
- Data Source
  KAKENHI-PROJECT-18656101
[Journal Article] 時間冗長ビットシリアル多値演算に基づくユニバーサルVLSI2006
- Author(s)
  伊藤祐, 亀山充隆
- Journal Title
  
  電気関係学会東北支部連合大会 IF12
  
  Pages: 211-211
- NAID
  130005444056
- Data Source
  KAKENHI-PROJECT-18656101
[Journal Article] GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design2006
- Author(s)
  Waidyasooriya Hasitha Muthumala, Masanori Hariyama, and Michitaka, Kameyama
- Journal Title
  
  IEEE Asia Pacific Conference on Circuits and Systems
  
  Pages: 1266-1269
- NAID
  110006291420
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design2006
- Author(s)
  Waidyasooriya Hasitha Muthumala, Masanori Hariyama, andMichitaka, Kameyama
- Journal Title
  
  IEEE Asia Pacific Conference on Circuits and Systems
  
  Pages: 1266-1269
- NAID
  110006291420
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] シリーズゲーティングに基づく多値ソースカッブルドロジックリコンフィギャラブルVLSIの構成2006
- Author(s)
  岡田信彬, Haque Mohammad Munirul, 亀山充隆
- Journal Title
  
  電気関係学会東北支部連合大会 IF13
  
  Pages: 212-212
- Data Source
  KAKENHI-PROJECT-18656101
[Journal Article] Dynamically Reconfigurable Gate Array Based on Fine-Grained Switch Elements and Its CAD Environment2006
- Author(s)
  Masanori Hariyama, Waidyasooriya Hasitha Muthumala, and Michitaka Kameyama
- Journal Title
  
  Proc. Asian Solid-State Circuits Conference
  
  Pages: 155-158
- NAID
  120001182114
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Evaluation of Multiple-valued Packet Multiplexing Scheme forNetwork-on-Chip Architecture2006
- Author(s)
  Haque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama
- Journal Title
  
  International Symposium on Multiple-valued Logic (CD-ROM)
- NAID
  120001182129
- Data Source
  KAKENHI-PROJECT-18656101
[Journal Article] Dynamically Reconfigurable Gate Array Based on Fine-Grained Switch Elements and Its CAD Environment2006
- Author(s)
  Masanori Hariyama, Waidyasooriya Hasitha Muthumala, Michitaka Kameyama
- Journal Title
  
  Proc. Asian Solid-State Circuits Conference
  
  Pages: 155-158
- NAID
  120001182114
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates2006
- Author(s)
  Masanori HARIYAMA, Sho OGATA, Michitaka KAMEYAMA
- Journal Title
  
  IEICE Trans. Electron. Vol.E89-C,No.11
  
  Pages: 1655-1661
- NAID
  110007538704
- Data Source
  KAKENHI-PROJECT-18656101
[Journal Article] 多値・二値ハイブリッドコンテクストスイッチング信号を用いたマルチコンテクストFPGAのアーキテクチャ2006
- Author(s)
  中谷好博, 張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会技術報告 ICD2005-211
  
  Pages: 37-42
- NAID
  10017255603
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 1000frame/sec Stereo Matching VLSI Processor with Adaptive Window-Size Control2006
- Author(s)
  Masanori Hariyama, Naoto Yokoyama and Michitaka Kameyama
- Journal Title
  
  Proc. Asian Solid-State Circuits Conference
  
  Pages: 123-126
- NAID
  120001182113
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 最適スケジューリングに基づく3眼ステレオビジョンVLSIプロセッサの構成2006
- Author(s)
  横山直人, 張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会技術報告 ICD-2006-153
  
  Pages: 55-60
- NAID
  10018707021
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Processor Architecture for Road Extraction Based on Projective Transformation2006
- Author(s)
  Sunggae Lee, Masanori Hariyama and Michitaka Kameyama
- Journal Title
  
  SICE-ICCAS
  
  Pages: 1446-1450
- NAID
  110004748907
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors2006
- Author(s)
  MasanoriHariyama, Michitaka Kameyama, Yasuhiro Kobayashi
- Journal Title
  
  IEEE Computer Society Anual Symposium on VLSI
  
  Pages: 193-198
- NAID
  120001182132
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification2006
- Author(s)
  Masanori HARIYAMA, Shigeo YAMADERA, and Michitaka KAMEYAMA
- Journal Title
  
  IEICE Trans. Electron Vol. E89-C, No. 11
  
  Pages: 1551-1558
- NAID
  110007538691
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] ウィンドウ並列・ピクセル並列アーキテクチャに基づくステレオビジョンプロセッサ2006
- Author(s)
  横山直人, 張山昌論, 小林康浩, 亀山充隆
- Journal Title
  
  電子情報通信学会技術報告 ICD2005-212
  
  Pages: 43-46
- NAID
  10017255609
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Real-Time Register-Transfer-Level Optimization for a Dynamically Reconfigurable VLSI Processor2006
- Author(s)
  Yonanda Adhitama, Michitaka Kameyama
- Journal Title
  
  IEEE International Conference on Computers and Devices for Communication (CD-ROM)
- Data Source
  KAKENHI-PROJECT-18656101
[Journal Article] Fine-Grain Cell Design for Multiple-valued Reconfigurable VLSI Using a Single Differential-Pair Circuit2006
- Author(s)
  Haque Mohammad Munirul, Michitaka Kameyama
- Journal Title
  
  International Symposium on Multiple-valued Logic (CD-ROM)
- Data Source
  KAKENHI-PROJECT-18656101
[Journal Article] Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification2006
- Author(s)
  MasanoriHARIYAMA, Shigeo YAMADERA, Michitaka KAMEYAMA
- Journal Title
  
  IEICE Trans. Electron. Vol.E89-C, No.11
  
  Pages: 1551-1558
- NAID
  110007538691
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design2006
- Author(s)
  Waidyasooriya Hasitha Muthumala, Masanori Hariyama, Michitaka, Kameyama
- Journal Title
  
  IEEE Asia Pacific Conference on Circuits and Systems
  
  Pages: 1266-1269
- NAID
  110006291420
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Minimizing Energy Consumption of VLSI Processors Based on Dual-Supply-Voltage Assignment and Interconnection Simpoification2005
- Author(s)
  Masanori Hariyama, Shigeo Yamadera and Michitaka Kameyama
- Journal Title
  
  Proc. 48th IEEE International Midwest Symposium on Circuits and Systems
  
  Pages: 1867-1870
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] FPGAImplementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture2005
- Author(s)
  Masanori Hariyama, Yasuhiro Kobayashi, Haruka Sasaki, and Michitaka Kameyama
- Journal Title
  
  IEICE Trans. Fundamentals Vol.E88-A,No.12
  
  Pages: 3516-3522
- NAID
  110004019457
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] ウィンドウ並列・ピクセル並列スケジューリングに基づく高信頼ステレオマッチングVLSIのアーキテクチャ2005
- Author(s)
  横山直人, 張山昌論, 亀山充隆
- Journal Title
  
  電気関係学会東北支部連合大会 2I8
  
  Pages: 328-328
- NAID
  130005443855
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 対応点探索と差分画像処理に基づく道路抽出アルゴリズム2005
- Author(s)
  李承啓, 張山昌論, 亀山充隆
- Journal Title
  
  電気関係学会東北支部連合大会 2G14
  
  Pages: 260-260
- NAID
  130005443759
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Novel Switch Block Architecture Using Non-Volatile Functional Pass-gate for Multi-Context FPGAs2005
- Author(s)
  Masanori Hariyama, Weisheng Chong, Sho Ogata, Michitaka Kameyama
- Journal Title
  
  Proc. IEEE Computer Society Annual Conference on vlsi
  
  Pages: 46-50
- NAID
  120001182131
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Derivation of Performance Specification of Intelligent Integrated Systems in Environment of Human-Computer Interaction2005
- Author(s)
  Yuta Sakai, Michitaka Kameyama
- Journal Title
  
  The IASTED International Conference on Human-Computer Interaction
  
  Pages: 161-166
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages2005
- Author(s)
  Masanori Hariyama, Tetsuya Aoyama, and Michitaka Kameyama
- Journal Title
  
  IEEE Transaction on Computers Vol.54,No.6
  
  Pages: 642-650
- NAID
  120001182139
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Intelligent Integrated Systems for Human-Oriented Information Society2005
- Author(s)
  Michitaka Kameyama
- Journal Title
  
  GSIS International Symposium on Information Sciences of New Era
  
  Pages: 77-103
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Design of Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate2005
- Author(s)
  Masanori Hariyama, Sho Ogata, Michitaka Kameyama, Yasutoshi Morita
- Journal Title
  
  IEEE Asian Solid-State Circuits Conference(A-SSCC)
  
  Pages: 421-424
- NAID
  120001182112
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Low-Power Field-Programmalble VLSI Using Multiple Supply Voltages2005
- Author(s)
  Weisheng Chong, Masanori Hariyama, Michitaka Kameyama
- Journal Title
  
  IEICE Trans. Fundamentals Vol. E88-A No. 12
  
  Pages: 3298-3305
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Low-Power Field-Programmalble VLSI Using Multiple Supply Voltages2005
- Author(s)
  Weisheng Chong, Masanori Hariyama, Michitaka Kameyama
- Journal Title
  
  IEICE Trans. Fundamentals Vol.E88-A No.12,
  
  Pages: 3298-3305
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] DSP-Specific Field-Programmable VLSI and Its CAD Environment2005
- Author(s)
  Masanori Hariyama, Sho Ogata, and Michitaka Kameyama
- Journal Title
  
  Proc. 48th IEEE International Midwest Symposium on Circuits and Systems
  
  Pages: 651-654
- NAID
  120001182135
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architectgure2005
- Author(s)
  Masanori Hariyama, Yasuhiro Kobayashi, naoto Yokoyama, and Michitaka Kameyama
- Journal Title
  
  Proc. 48th IEEE International Midwest Symposium on Circuits and Systems
  
  Pages: 1219-1222
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory2005
- Author(s)
  Weisheng Chong, Sho Ogata, Masanori Hariyama and Michitaka Kameyama
- Journal Title
  
  Proc. International Parallel and Distributed Processing Symposium CD-ROM
- NAID
  110003318215
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 機能パスゲートを用いたマルチコンテクストFPGA2005
- Author(s)
  中谷好博, 張山昌論, 亀山充隆
- Journal Title
  
  電気関係学会東北支部連合大会 2I9
  
  Pages: 329-329
- NAID
  130005443858
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access2005
- Author(s)
  Masanori Hariyama, Haruka Sasaki, and Michitaka Kameyama
- Journal Title
  
  IEICE Trans. Inf. & Syst. Vol.E88-D,No.7
  
  Pages: 1486-1491
- NAID
  110003214339
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Design of Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic2005
- Author(s)
  Akira Mochizuki, Takahiro Hanyu, Michitaka Kameyama
- Journal Title
  
  Journal of Multiple-Valued Logic & Soft Computing Vol.11, Nos.5-6
  
  Pages: 481-497
- Data Source
  KAKENHI-PROJECT-16656103
[Journal Article] Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages2005
- Author(s)
  Masanori Hariyama, Tetsuya Aoyama, Michitaka Kameyama
- Journal Title
  
  IEEE Transaction on Computers Vol.54, No.6
  
  Pages: 642-650
- NAID
  120001182139
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Minimizing Energy Consumption of VLSI Processors Based on Dual-Supply-Voltage Assignment and Interconnection Simpoification2005
- Author(s)
  Masanori Hariyama, Shigeo Yamadera, Michitaka Kameyama
- Journal Title
  
  Proc.48th IEEE International Midwest Symposium on Circuits and Systems
  
  Pages: 3201-3201
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 高安全知能自動車用VLSIプロセッサの性能仕様の決定法2005
- Author(s)
  坂井勇太, 亀山充隆
- Journal Title
  
  第5回計測自動制御学会制御部門大会
  
  Pages: 1-4
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Real-Time High-Level Synthesis for a Dynamically Reconfigurable VLSI Processor2005
- Author(s)
  Adhitama Yonanda, 亀山充隆
- Journal Title
  
  電気関係学会東北支部連合大会 1A02
  
  Pages: 2-2
- NAID
  130005443846
- Data Source
  KAKENHI-PROJECT-16656103
[Journal Article] Derivation of Performance Speciflcation of Intelligent Integrated Systems in Environment of Human-Computer Interaction2005
- Author(s)
  Yuta Sakai and Michi taka Kameyama
- Journal Title
  
  The IASTED International Conference on Human-Computer Interaction
  
  Pages: 161-166
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Low-Power Field-Programmalble VLSI Using Multiple Supply Voltages2005
- Author(s)
  Weisheng Chong, Masanori Hariyama, Michitaka Kameyama
- Journal Title
  
  IEICE Trans.Fundamentals Vol.E88-A, No.12
  
  Pages: 3298-3305
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] VLSI Architecture Based on Packet Data Transfer Scheme and Its Application2005
- Author(s)
  Yuya Homma, Michitaka Kameyama, Yoshichika Fujioka, Nobuhiro Tomabechi
- Journal Title
  
  Proc.2005 IEEE International Symposium on Circuits and Systems
  
  Pages: 1786-1789
- NAID
  120001182128
- Data Source
  KAKENHI-PROJECT-16656103
[Journal Article] FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture2005
- Author(s)
  Masanori Hariyama, Yasuhiro Kobayashi, Haruka Sasaki, Michitaka Kameyama
- Journal Title
  
  IEICE Trans.Fundamentals Vol.E88-A, No.12
  
  Pages: 3516-3522
- NAID
  110004019457
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture2005
- Author(s)
  Masanori Hariyama, Yasuhiro Kobayashi, Naoto Yokoyama, Michitaka Kameyama
- Journal Title
  
  Proc.48th IEEE International Midwest Symposium on Circuits and Systems
  
  Pages: 3194-3194
- NAID
  110004019457
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access2005
- Author(s)
  Masanori Hariyama, Haruka Sasaki, Michitaka Kameyama
- Journal Title
  
  IEICE Trans.Inf.& Syst. Vol.E88-D, No.7
  
  Pages: 1486-1491
- NAID
  110003214339
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Logic-in-Memory VLSI circuit for Fully Paralle Nearest Pattern Matching Based on Floating-Gate-MOS Pass-Transistor Logic2005
- Author(s)
  Takahiro Hanyu, Shunichi Kaeriyama, Michitaka Kameyama
- Journal Title
  
  Journal of Multiple-Valued Logic & Soft Computing Vol.11, Nos.5-6
  
  Pages: 619-632
- Data Source
  KAKENHI-PROJECT-16656103
[Journal Article] Design of Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate2005
- Author(s)
  Masanori Hariyama, Sho Ogata, and Michitaka Kameyama, yasutoshi Morita
- Journal Title
  
  IEEE Asian Solid-State Circuits Conference(A-SSCC)
  
  Pages: 421-424
- NAID
  120001182112
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Novel Switch Block Architecture Using Non-Volatile Functional Pass-gate for Multi-Context FPGAs2005
- Author(s)
  Masanori Hariyama, Weisheng Chong, Sho Ogata, Michitaka Kameyama
- Journal Title
  
  Proc. IEEE Computer Society Annual Conference on VLSI
  
  Pages: 46-50
- NAID
  120001182131
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Genetic Approach to Minimizing Energy Consumption of VLSI Processors using Multiple Supply voltages2005
- Author(s)
  Masanori Hariyama, Tetsuya Aoyama, and Michitaka Kameyama
- Journal Title
  
  IEEE Transaction on Computers Vol. 54, No. 6
  
  Pages: 642-650
- NAID
  120001182139
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] DSP-Specific Field-Programmable VLSI and Its CAD Environment2005
- Author(s)
  Masanori Hariyama, Sho Ogata, Michitaka Kameyama
- Journal Title
  
  Proc.48th IEEE International Midwest Symposium on Circuits and Systems
  
  Pages: 3199-3199
- NAID
  120001182135
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Derivation of Performance Specification of Intelligen Integrated Systems in Environment of Human-Computer Interaction2005
- Author(s)
  Yuta Sakai and Michitaka Kameyama
- Journal Title
  
  The IASTED International Conference on Human-Computer Interaction
  
  Pages: 161-166
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 確率と物理モデルに基づく高安全知能自動車の軌道予測システム2005
- Author(s)
  Nguyen Van Dan, 亀山充隆
- Journal Title
  
  電気関係学会東北支部連合大会 2E26
  
  Pages: 197-197
- NAID
  130005443740
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access2005
- Author(s)
  Masanori Hariyama, Haruka Sasaki, and Michitaka Kameyama
- Journal Title
  
  ELCE Trans. Inf. & Syst Vol. E88-D, No. 7
  
  Pages: 1486-1491
- NAID
  110003214339
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architectgure2005
- Author(s)
  Masanori Hariyama, Yasuhiro Kobayashi, Naoto Yokoyama, and Michitaka Kameyama
- Journal Title
  
  Proc. 48th IEEE International Midwest Symposlum on Circuits and Systems
  
  Pages: 1219-1222
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] "Intelligent Integrated Systems for Human-Oriented Information Society2005
- Author(s)
  Michitaka Kameyama
- Journal Title
  
  GSIS International Symposium on Information Sciences of New Era
  
  Pages: 77-103
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory2005
- Author(s)
  Weisheng Chong, Sho Ogata, Masanori Haariyama, Michitaka Kameyama
- Journal Title
  
  Proc.International Parallel and Distributed Processing Symposium
- NAID
  110003318215
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory2005
- Author(s)
  Weisheng Chong, Sho Ogata, masanori hariyama and Michitaka Kameyama
- Journal Title
  
  Proc. International Parallel and Distributed Processing Symposium, CD-ROM (CD-ROM)
- NAID
  110003318215
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] FPGAImplementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture2005
- Author(s)
  Masanori Hariyama, yasuhiroKobayashi, Haruka Sasaki, and Michitaka Kameyama
- Journal Title
  
  IEICE Trans. Fundamentals Vol. E88-A, No. 12
  
  Pages: 3516-3522
- NAID
  110004019457
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer2005
- Author(s)
  Tomoaki Hasegawa, Yuya Homma, Michitaka Kameyama
- Journal Title
  
  Proc.of the 35th IEEE International Symposium on Multiple-Valued Logic
  
  Pages: 114-119
- Data Source
  KAKENHI-PROJECT-16656103
[Journal Article] Real-Time Threshold-Voltage Control Scheme for Low-Power VLSI Under Fluctuation of a Supply Voltage2005
- Author(s)
  Ahmed Shaheer, Michitaka Kameyama
- Journal Title
  
  Proc.IEEE International Symposium on Signals, Circuits and Systems
  
  Pages: 15-18
- Data Source
  KAKENHI-PROJECT-16656103
[Journal Article] Intelligent Integrated Systems for Human-Oriented Information Society2005
- Author(s)
  Michitaka Kameyama
- Journal Title
  
  GSIS International Symposium on Information Sciences of New Era
  
  Pages: 77-103
- Data Source
  KAKENHI-PROJECT-16656103
[Journal Article] Implementation and Evaluation of a Fine-Grain Multiple-Valued Field-Programmable VLSI Based on Source-Coupled Logic2005
- Author(s)
  Haque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama
- Journal Title
  
  Proc.of the 35th IEEE International Symposium on Multiple-Valued Logic
  
  Pages: 120-125
- Data Source
  KAKENHI-PROJECT-16656103
[Journal Article] Design of Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate2005
- Author(s)
  Masanori Hariyama, Sho Ogata, and Michitaka Kameyama, Yasutoshi Morita
- Journal Title
  
  IEEE Asian Solid-State Circuits Conference (A-SSCC)
  
  Pages: 421-424
- NAID
  120001182112
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Novel Switch Block Architecture Using Non-Volatile Functional Pass-gate for Multi-Context FPGAs2005
- Author(s)
  Masanori Hariyama, Weisheng Chong, Sho Ogata, Michitaka Kameyama
- Journal Title
  
  Proc.IEEE Computer Society Annual Conference on VLSI
  
  Pages: 46-50
- NAID
  120001182131
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] パケット転送に基づくVLSIアーキテクチャと多値集積化2004
- Author(s)
  本間悠也, 亀山充隆
- Journal Title
  
  多値論理研究ノート Vol.27, No.7
- Data Source
  KAKENHI-PROJECT-16656103
[Journal Article] Complementary Ferroelectric-Capacitor Logic for Low-PowerLogic-in-Memory VLSI2004
- Author(s)
  H.Kimura, T.Hanyu, M.Kameyama, Y.Fujimori, T.Nakamura, H.Takasu
- Journal Title
  
  IEEE J.Solid-State Circuits vol.39, no.6
  
  Pages: 919-926
- Data Source
  KAKENHI-PROJECT-16656103
[Journal Article] Ultra-Fine-Grain Field-Programmable VLSI Using Multiple-Valued Source-Coupled Logic2004
- Author(s)
  Haque Mohammad Munirul, Michitaka Kameyama
- Journal Title
  
  Proc.34th IEEE International Symposium on Multiple-Valued Logic
  
  Pages: 26-30
- Data Source
  KAKENHI-PROJECT-16656103
[Journal Article] 細粒度多値フィールドプログラマブルVLSIの論理構成2004
- Author(s)
  長谷川智亮, 亀山充隆
- Journal Title
  
  電子関係学会東北支部連合大会 2G19
  
  Pages: 264-264
- NAID
  130005443530
- Data Source
  KAKENHI-PROJECT-16656103
[Journal Article] リアルタイム最適制御に基づくVLSIプロセッサの低電力化2004
- Author(s)
  Ahmad Shaheer, 亀山充隆
- Journal Title
  
  計測自動制御学会東北支部第219回研究集会 No.219-7
  
  Pages: 1-5
- Data Source
  KAKENHI-PROJECT-16656103
[Journal Article] Multiple-Valued Source-Coupled Logic VLSI Based on Adaptive Threshold Control and Its Applications2004
- Author(s)
  Haque Mohammad Munirul, Michitaka Kameyama
- Journal Title
  
  Proc.34th IEEE International Symposium on Multiple-Valued Logic
  
  Pages: 328-333
- Data Source
  KAKENHI-PROJECT-16656103
[Journal Article] Architecture of a Fine-Grain Filed-Programmabel VLSI Based on Multiple-Valued Source-Coupled Logic2004
- Author(s)
  Md.Munirul HAQUE, Michitaka KAMEYAMA
- Journal Title
  
  IEICE Transactions on Electronics Vol.E87-C, No.11
  
  Pages: 1869-1875
- Data Source
  KAKENHI-PROJECT-16656103
[Journal Article] VLSI Architecture Based on Real-Time Power Minimization Scheme2004
- Author(s)
  Ahmad Shaheer, Michitaka Kameyama
- Journal Title
  
  電子関係学会東北支部連合大会 2E4
  
  Pages: 179-179
- NAID
  130004677292
- Data Source
  KAKENHI-PROJECT-16656103
[Journal Article] Design and Evaluation of Fine-Grain Field-Programmable VLSI Based on Multiple-Valued Source-Coupled Logic2004
- Author(s)
  Md.Munirul Haque, Michitaka Kameyama
- Journal Title
  
  電子情報通信学会技術研究報告 ICD2004-193〜199
  
  Pages: 37-40
- NAID
  110003318228
- Data Source
  KAKENHI-PROJECT-16656103
[Presentation] 新しい概念のＶＬＳＩコンピューティングとその応用を目指して2016
- Author(s)
  亀山充隆
- Organizer
  第２９回多値論理とその応用研究会
- Place of Presentation
  東北大学（仙台市）
- Year and Date
  2016-01-09
- Invited
- Data Source
  KAKENHI-PROJECT-26630145
[Presentation] マルチプレクサロジックに基づく細粒度リコンフィギャラブルVLSIの構成2015
- Author(s)
  島袋勝彦，亀山充隆
- Organizer
  第38回多値論理フォーラム
- Place of Presentation
  北海道大学(札幌市）
- Year and Date
  2015-09-13
- Data Source
  KAKENHI-PROJECT-26630145
[Presentation] 危険要素抽出の高精度化に基づく高安全知能システムの構成2015
- Author(s)
  大河原茂樹，亀山充隆
- Organizer
  情報処理学会第77回全国大会
- Place of Presentation
  京都大学（京都府京都市）
- Year and Date
  2015-03-18
- Data Source
  KAKENHI-PROJECT-25280011
[Presentation] 危険要素抽出に基づく高安全システムの高品質化とVLSIプラットフォーム2015
- Author(s)
  大河原茂樹，亀山充隆
- Organizer
  FIT 情報科学技術フォーラム
- Place of Presentation
  愛媛大学（松山市）
- Year and Date
  2015-09-17
- Data Source
  KAKENHI-PROJECT-25280011
[Presentation] 高安全知能システム用リコンフィギャラブルプロセッサのアーキテクチャ2015
- Author(s)
  大河原茂樹，亀山充隆, 藤岡与周
- Organizer
  電気関係学会東北支部連合大会
- Place of Presentation
  岩手県立大学(滝沢市）
- Year and Date
  2015-08-28
- Data Source
  KAKENHI-PROJECT-25280011
[Presentation] リアルワールド応用知能システムとそのVLSIコンピューティングプラットフォームの展望2015
- Author(s)
  亀山充隆
- Organizer
  電子情報通信学会集積回路研究会
- Place of Presentation
  岩松旅館（仙台市青葉区）
- Year and Date
  2015-10-27
- Invited
- Data Source
  KAKENHI-PROJECT-25280011
[Presentation] Prospects of Computing Platform for Real-World Intelligent Systems2015
- Author(s)
  Michitaka Kameyama
- Organizer
  International Conference on Information and Digital Technologies 2015
- Place of Presentation
  Zilina, Slovakia
- Year and Date
  2015-07-09
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280011
[Presentation] 高安全知能システムの高品質化とVLSIコンピューティングプラットフォーム2015
- Author(s)
  大河原茂樹，亀山充隆,　藤岡与周,
- Organizer
  第３８回多値論理フォーラム
- Place of Presentation
  北海道大学（札幌市）
- Year and Date
  2015-09-13
- Data Source
  KAKENHI-PROJECT-25280011
[Presentation] マイクロパケット転送方式に基づく多値リコンフィギャラブルVLSIの構成と評価2014
- Author(s)
  原田伸太郎，亀山充隆,　藤岡与周
- Organizer
  第37回多値論理フォーラム
- Place of Presentation
  関西大学（大阪府吹田市）
- Year and Date
  2014-09-13
- Data Source
  KAKENHI-PROJECT-26630145
[Presentation] 危険要素の抽出に基づく高安全知能システム2014
- Author(s)
  大河原茂樹，Lukac Martin，亀山充隆
- Organizer
  平成26年電気関係学会東北支部連合大会
- Place of Presentation
  山形大学（山形県米沢市）
- Year and Date
  2014-08-22
- Data Source
  KAKENHI-PROJECT-25280011
[Presentation] LEDR/4相2線ハイブリッドアーキテクチャに基づく高性能非同期FPGA2014
- Author(s)
  小松与志也，張山昌論，亀山充隆
- Organizer
  電子情報通信学会リコンフィギャラブルシステム研究会
- Place of Presentation
  東北大学片平さくらホール（宮城県仙台市）
- Year and Date
  2014-06-12
- Data Source
  KAKENHI-PROJECT-25280011
[Presentation] コンフィグレーションメモリサイズの減少を指向したパケット転送に基づく動的再構成VLSIプロセッサの構成2012
- Author(s)
  藤岡周与,亀山充隆
- Organizer
  電子情報通信学会技術報告,ICD2012-64,pp.39-44
- Place of Presentation
  ホテルルイズ(盛岡),岩手
- Year and Date
  2012-10-19
- Data Source
  KAKENHI-PROJECT-23656230
[Presentation] X-Netを用いた多値データ転送方式とリコンフィギャラブルVLSIへの応用2012
- Author(s)
  白旭,亀山充隆
- Organizer
  多値論理研究ノート,Vol.35,No.5,pp.5-1-5-6
- Place of Presentation
  富山国際会議場大手町フォーラム,富山
- Year and Date
  2012-09-15
- Data Source
  KAKENHI-PROJECT-23656230
[Presentation] 電流源自律制御に基づく低電力多値VLSIとその応用2012
- Author(s)
  木皿祥吾,亀山充隆
- Organizer
  多値論理研究ノート,Vol.35,No.6,pp.6-1-6-5
- Place of Presentation
  富山国際会議場大手町フォーラム,富山
- Year and Date
  2012-09-15
- Data Source
  KAKENHI-PROJECT-23656230
[Presentation] 多値スイッチブロックと2値論理演算モジュールから構成されるビットシリアルリコンフィギャラブルVLSI2011
- Author(s)
  白旭,亀山充隆
- Organizer
  多値論理研究ノート,Vol.34,No.9,pp.9-1-9-8
- Place of Presentation
  つくば国際会議場,茨城
- Year and Date
  2011-09-18
- Data Source
  KAKENHI-PROJECT-23656230
[Presentation] Prospects of Post-Binary ULSI Systems and Novel Reconfigurable VLSI Architectures2011
- Author(s)
  Michitaka Kameyama
- Organizer
  The 20th International Workshop on Post-Binary ULSI Systems (Invited Talk)(招待講演)
- Place of Presentation
  Tusula, Finland
- Data Source
  KAKENHI-PROJECT-23656230
[Presentation] レジスタトランスファレベルパケット転送に基づく動的再構成VLSIプロセッサアーキテクチャ2011
- Author(s)
  藤岡与周,瀧沢翔,亀山充隆
- Organizer
  電子情報通信学会技術研究報告,ICD2011-67,pp14-18
- Place of Presentation
  一の坊,宮城
- Year and Date
  2011-10-24
- Data Source
  KAKENHI-PROJECT-23656230
[Presentation] Prospects ofPost-Binary ULSI Systems and NovelReconfigurable VLSI Architectures2011
- Author(s)
  Michitaka Kameyama
- Organizer
  The 20th International Workshop on Post-Binary ULSI Systems (Invited Talk)
- Place of Presentation
  Tusula, Finland
- Year and Date
  2011-05-22
- Data Source
  KAKENHI-PROJECT-23656230
[Presentation] High-Performance Digit-Serial Multiple-Valued Reconfigurable VLSI Utilizing Sharing of Differential-Pair-Circuit Current Sources2011
- Author(s)
  Xu Bai, Nobuaki Okada, Michitaka Kameyama
- Organizer
  多値論理とその応用研究会
- Place of Presentation
  東北大学(仙台市)
- Year and Date
  2011-01-08
- Data Source
  KAKENHI-PROJECT-21656088
[Presentation] 自律的電流源制御に基づく低電力多値VLSIの構成2011
- Author(s)
  木皿祥吾,亀山充隆
- Organizer
  電気関係学会東北支部連合大会,2H01,p.265
- Place of Presentation
  東北学院大学多賀城キャンパス,宮城
- Year and Date
  2011-08-26
- Data Source
  KAKENHI-PROJECT-23656230
[Presentation] 入力到来とクロックサイクル内論理演算完了の検出に基づく低電力多値リコンフィギャラブルVLSIの自律電流源制御2011
- Author(s)
  木皿祥吾,亀山充隆
- Organizer
  多値論理研究ノート,Vol.34,No.10,pp.10-1-10-5
- Place of Presentation
  つくば国際会議場,茨城
- Year and Date
  2011-09-18
- Data Source
  KAKENHI-PROJECT-23656230
[Presentation] Low-Power Multiple-Valued Reconfigurable VLSI Based on Superposition of Bit-Serial Data and Current-Source Control Signals2010
- Author(s)
  Akitaka Ishikawa, Nobuaki Okada, Michitaka Kameyama
- Organizer
  40th IEEE International Symposium on Multiple-Valued Logic
- Place of Presentation
  Barcelona (Spain)
- Year and Date
  2010-05-27
- Data Source
  KAKENHI-PROJECT-21656088
[Presentation] High-performance Multiple-valued Reconfigurable VLSI Using Logic Blocks with High-Driving Capability2010
- Author(s)
  Xu Bai, Nobuaki Okada, Michitaka Kameyama
- Organizer
  電気関係学会東北支部連合大会
- Place of Presentation
  八戸工業大学(八戸市)
- Year and Date
  2010-08-26
- Data Source
  KAKENHI-PROJECT-21656088
[Presentation] データ・電流源制御信号のビットシリアル転送に基づく多値VLSIの構成2009
- Author(s)
  石川彰隆, 岡田信彬, 亀山充隆
- Organizer
  電気関係学会東北支部連合大会
- Place of Presentation
  東北文化学園大学(仙台)
- Year and Date
  2009-08-20
- Data Source
  KAKENHI-PROJECT-21656088
[Presentation] Multiple-Valued Reconfigurable VLSI Processor Based on Superposition of Data and Control Signals2009
- Author(s)
  Nobuaki Okada, Michitaka Kameyama
- Organizer
  Proceedings of the 39th IEEE International Symposium on Multiple-Valued Logic
- Place of Presentation
  Naha(Okinawa)
- Year and Date
  2009-05-21
- Data Source
  KAKENHI-PROJECT-21656088
[Presentation] Design of a Fine-Grain Reconfigurable VLSI Based on Logic-In-Control Architecture2009
- Author(s)
  Nobuaki Okada, Michitaka Kameyama
- Organizer
  Proc.the 2009 International SoC Design Conference
- Place of Presentation
  Pusan(Korea)
- Year and Date
  2009-11-24
- Data Source
  KAKENHI-PROJECT-21656088
[Presentation] レジスタトランスファレベルパケット転送に基づく動的再構成VLSIプロセッサアーキテクチャ
- Author(s)
  藤岡与周, 瀧沢翔, 亀山充隆
- Organizer
  電子情報通信学会技術研究報告, ICD2011-67, pp14-18(2011)
- Place of Presentation
  一の坊、宮城
- Data Source
  KAKENHI-PROJECT-23656230
[Presentation] X-Netを用いた多値データ転送方式とリコンフィギャラブルVLSIへの応用
- Author(s)
  白旭, 亀山充隆
- Organizer
  多値論理研究ノート, Vol.35, No.5, pp.5-1 - 5-6(2012)
- Place of Presentation
  富山国際会議場大手町フォーラム、富山
- Data Source
  KAKENHI-PROJECT-23656230
[Presentation] 多値スイッチブロックと２値論理演算モジュールから構成されるビットシリアルリコンフィギャラブルVLSI
- Author(s)
  白　旭, 亀山充隆
- Organizer
  多値論理研究ノート, Vol.34, No.9, pp.9-1 - 9-8(2011)
- Place of Presentation
  つくば国際会議場、茨城
- Data Source
  KAKENHI-PROJECT-23656230
[Presentation] 電流モード論理に基づく多値細粒度リコンフィギャラブルVLSIの新概念アーキテクチャ
- Author(s)
  白旭, 亀山充隆
- Organizer
  電子情報通信学会集積回路研究会（ICD）
- Place of Presentation
  弘前大学コラボ弘大八甲田ホール
- Data Source
  KAKENHI-PROJECT-25280011
[Presentation] 入力到来とクロックサイクル内論理演算完了の検出に基づく低電力多値リコンフィギャラブルVLSIの自律電流源制御
- Author(s)
  木皿祥吾, 亀山充隆
- Organizer
  多値論理研究ノート, Vol.34, No.10, pp.10-1 - 10-5(2011)
- Place of Presentation
  つくば国際会議場、茨城
- Data Source
  KAKENHI-PROJECT-23656230
[Presentation] コンフィグレーションメモリサイズの減少を指向したパケット転送に基づく動的再構成VLSIプロセッサの構成
- Author(s)
  藤岡周与，亀山充隆
- Organizer
  電子情報通信学会技術報告, ICD2012-64, pp.39-44 (2012）
- Place of Presentation
  ホテルルイズ（盛岡）、岩手
- Data Source
  KAKENHI-PROJECT-23656230
[Presentation] パケット転送制御に基づくロジックインメモリ構造多値リコンフィギャラブルVLSI
- Author(s)
  原田伸太郎，白　旭，藤岡与周，亀山充隆
- Organizer
  平成25年度電気関係学会東北支部連合大会
- Place of Presentation
  会津大学
- Data Source
  KAKENHI-PROJECT-25280011
[Presentation] 電流源自律制御に基づく低電力多値VLSIとその応用
- Author(s)
  木皿祥吾, 亀山充隆
- Organizer
  多値論理研究ノート, Vol.35, No.6, pp.6-1 - 6-5(2012)
- Place of Presentation
  富山国際会議場大手町フォーラム、富山
- Data Source
  KAKENHI-PROJECT-23656230
[Presentation] ビットシリアルパケット転送に基づくロジックインメモリ多値リコンフィギャラブルVLSI
- Author(s)
  原田伸太郎，白旭，藤岡与周, 亀山充隆
- Organizer
  第36回多値論理フォーラム（姫路）
- Place of Presentation
  姫路市市民会館
- Data Source
  KAKENHI-PROJECT-25280011
[Presentation] 自律的電流源制御に基づく低電力多値VLSIの構成
- Author(s)
  木皿祥吾,亀山充隆
- Organizer
  電気関係学会東北支部連合大会, 2H01,p.265(2011)
- Place of Presentation
  東北学院大学多賀城キャンパス、宮城
- Data Source
  KAKENHI-PROJECT-23656230

1. HANYU Takahiro (40192702)

# of Collaborated Projects: 12 results

# of Collaborated Products: 0 results
2. HIGUCHI Tatsuo (20005317)

# of Collaborated Projects: 6 results

# of Collaborated Products: 0 results
3. HARIYAMA Masanori (10292260)

# of Collaborated Projects: 5 results

# of Collaborated Products: 69 results
4. OHMI Tadahiro (20016463)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
5. TSUBOUTI Kazuo (30006283)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
6. ISHIWARA Hiroshi (60016657)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
7. ASADA Kunihiro (70142239)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
8. HORIIKE Yasuhiro (20209274)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
9. KANOMATA AKIO (20044654)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
10. SMITH Kenneth C.

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
11. TOMABECHI Nobuhiro (70048180)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
12. UCHIYAMA Masaru (30125504)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
13. SASAO Tsutomu (20112013)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
14. TERADA Hiroaki (80028985)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
15. TAMARU Keikichi (10127102)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
16. YASUURA Hiroto (80135540)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
17. TOHMA Yoshihiro (50016317)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
18. XIAOWEI Deng (70261576)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
19. MOCHIZUKI Akira (40359542)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
20. KIMURA Hiromitsu (00361155)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
21. 米田友洋 (30182851)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
22. 川人祥二 (40204763)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
23. NAKAMURA Yoshihiko

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
24. BUTLER Jon T.

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
25. LIN H.C.

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
26. NG Wai-Tung

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
27. GULAK Glenn

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
28. 内山勝

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
29. エドアルドバヨ

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
30. ドシェピエール

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
31. BAYO Eduardo

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
32. DAUCHEZ Pierre

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
33. SILIO Charle

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
34. SILIO Carles B.

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
35. CHARLES B Si

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
36. JON T Butler

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
37. KENNETH C Sm

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
38. NG Wai Tung

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
39. SMITH Rennet

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results

KAMEYAMA Michitaka 亀山 充隆

Research Projects

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Co-Researchers

Development of a Data-Transfer-Bottleneck-Free Nonvolatile Logic-In-Memory Multiple-Valued VLSIPrincipal Investigator

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Design of a Universal VLSI Platform for Highly-Safe Intelligent Systems ApplicationsPrincipal Investigator

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Multiple-Valued Reconfigurable VLSI Based on Adaptively Autonomous OperationPrincipal Investigator

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ロジックインコントロール多値リコンフィギャラブルVLSIPrincipal Investigator

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自律適応制御を指向したプログラマブルロジックインメモリVLSIPrincipal Investigator

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Optimal VLSI Design for a Highly-Safe Intelligent Vehicle Based on a System Integration TheoryPrincipal Investigator

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超並列リコンフィギャラブル多値VLSIコンピューティングに関する研究Principal Investigator

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Interconnection-Bottleneck-Free VLSI System Based on Dual-Rail Multiple-Valued Digital ComputingPrincipal Investigator

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Development of VLSI Processor Chip Family for Highly-Safe Intelligent Vehicles Based on Optimal Design MythologiesPrincipal Investigator

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High-Level Synthesis of High-Performance VLSI Processors for Intelligent Integrated SystemPrincipal Investigator

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KAMEYAMA Michitaka 亀山充隆