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YONEDA Tomohiro  米田 友洋

ORCIDConnect your ORCID iD *help
… Alternative Names

米田 友洋  ヨネダ トモヒロ

TONEDA Tomohiro  米田 友洋

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Researcher Number 30182851
Other IDs
External Links
Affiliation (Current) 2025: 国立情報学研究所, アーキテクチャ科学研究系, 教授
Affiliation (based on the past Project Information) *help 2013 – 2022: 国立情報学研究所, アーキテクチャ科学研究系, 教授
2016: 国立情報学研究所, 大学共同利用機関等の部局等, 教授
2012: 国立情報学研究所, アーキテクチャ研究系, 教授
2008 – 2011: National Institute of Informatics, アーキテクチャ科学研究系, 教授
2004: 情報・システム研究機構 国立情報学研究所, 情報基盤研究系, 教授 … More
2002 – 2004: National Institute of Informatics, Infrastructure Systems Research Division, Professor, 情報基盤研究系, 教授
2002: 国立情報学研究所, 教授
2001: 東京工業大学, 情報理工学研究科, 助教授
2000 – 2001: 東京工業大学, 大学院・情報理工学研究科, 助教授
1995 – 1998: 東京工業大学, 大学院・情報理工学研究科, 助教授
1994: 東京工業大学, 大学院情報理工学研究科, 助教授
1990 – 1994: 東京工業大学, 工学部, 助教授
1993: 東京工業大学, 工学部・情報工学科, 助教授
1988 – 1989: 東京工業大学, 工学部, 講師
1986: 東京工大, 工学部, 助手
1986: Tokyo Institute of Technology , Research Associate, 工学部, 助手 Less
Review Section/Research Field
Principal Investigator
計算機科学 / Computer system/Network / Communication/Network engineering / Computer system / 計算機工学 / Software
Except Principal Investigator
Computer system / 情報工学 / 計算機科学 / Medium-sized Section 60:Information science, computer engineering, and related fields / Science and Engineering / 計算機工学
Keywords
Principal Investigator
非同期式回路 / Partial order reduction / 形式的検証 / タイムペトリネット / Bounded delay model / Partial Order Reduction / 時間トレース理論 / 階層的検証 / クロック埋め込み / 低消費電力化 … More / シリアル通信 / 通信方式 / 同期/非同期インタフェース / 同期/非同期インタフェース / PLL/DLLレス / 4値レベル信号 / 細粒度パワーゲーティング / 高速シリアル通信 / Verilogシミュレーション / 再構成デバイス / 再構成可能デバイス / NoCルータ / 新フリップフロップ / 設計手法 / 遷移型 / Strongly fault-secure systems / Self-testing / Microprocessor design / Error secure interfaces Fault secure / Error propagating interfaces / Concurrnt error detection / Code disjoint / オンライン故障検出 / 超高信頼化システム / セルフチェッキングプロセッサ / フォールトトレラントシステム / 高信頼性 / 耐故障 / VLSI / アーキテクチャ / プロセッサ / 論理回路 / 検査回路 / 誤り伝搬性 / 誤り安全性 / セルフチェッキング / フォールトトレラント / Timed automaton / Real time software / Hierarchical verification / Level Time Petri net / レベルタイムペトリネット / 時間オートマトン / リアルタイムソフトウェア / Level Time Petri nets / Time Petri Nets / High level synthesis / Ternary dual-rail code / Formal Verification / Asynchronous Circuits / 3線式符号 / 3値論理回路 / 有限幅遅延モデル / 高位記述 / 3値2線式符号 / Timed trace theory / Time Petri nets / Asynchronous circuits / Formal verification / 有限遅延幅モデル / レイアウトのグルーピング / パス遅延情報 / レイアウトの最適化 / マッチドディレイの最適化 / 非同期式ネットワークオンチップルータ / マルチクロックフリップフロップ / 遷移型制御回路 / 束データ方式 / 遷移型制御 / 設計容易化 / 配置最適化 / 遅延値決定 / 最適化 / 非同期式設計 / ハードウェア化 / SVG / 非同期式回路設計 / 抽象化 / 帰納法 / パラメタライズ回路 / 定理証明器 / トレース理論 / 時相論理 / ペトリネット / 状態爆発 / リアルタイムシステム / 検証 … More
Except Principal Investigator
非同期式回路 / 不揮発性ロジック / 脳型ハードウェア / 計算機システム / Safety critical system / 論理回路 / セルフチェッキング / ばらつき補正機能 / はらつき補正機能 / MTJデバイス / ロジックLSI / 高速・低電力回路技術 / ダイ・ハード回路 / IoT応用 / ダーク・シリコンLSI / CMOS/MTJハイブリッド回路 / 不揮発ロジック / 脳型情報処理 / verification and synthesis of hardware / security of cryptographic primitives / secure system architecture / security protocol / network security analysis / safe program synthesis / specification analysis / インテグリティー解析 / 耐攻撃性 / セキュリティープロトコル / 実現可能性 / JAVA / インテグリティ解析 / DoS攻撃 / 検証 / コード生成 / 非同期回路 / Dos攻撃 / ネットワークセキュリティ / 暗号方式 / 安全性検証 / ハードウェアの安全性 / 暗号方式の安全性 / 安全なシステムアーキテクチャ / セキュリティプロトコル / ネットワークの安全性解析 / 安全なプログラム合成 / 仕様解析 / Asynchronous Circuit Testing / Asynchronous Logic Synthesis / ALSI System Design / Asynchronous VLSI System / Asynchronous Circuit / Asynchronous Processor / 非同期式回路テスト / 非同期式論理合成 / VLSIシステム設計 / 非同期式VLSIシステム / 非同期式プロセッサ / Grant system / Research fund / Academic research / 配分審査体制 / ヒアリング調査 / 研究費 / dependency graph / transition causality / delay models / two-rail two-phase / logic design / architecture / microprocessor / asynchronous circuits / 出力純粋遅延モデル / 依存性グラフ / 遷移因果律 / 遅延モデル / 2線2相式 / 論理設計 / アーキテクチャ / マイクロプロセッサ / Logic Synthesis / Logic Circuits / Processor Organization / Self-checking / Fault-tolerance / 論理式除算 / 論理合成 / プロセッサ方式 / フォ-ルトトレランス / テスト容易化設計 / VLSIテスト / 記憶・演算一体化 / マルチメディア応用 / Rambus / ISSCC / コミュニケーションVLSIプロセッサ / ニューパラダイムコンピユーティング / 高速データ転送技術 Less
  • Research Projects

    (21 results)
  • Research Products

    (20 results)
  • Co-Researchers

    (30 People)
  •  Development of a high-speed and ultra-low-power die-hard logic LSI fundamental technology for IoT applications

    • Principal Investigator
      羽生 貴弘
    • Project Period (FY)
      2021 – 2024
    • Research Category
      Grant-in-Aid for Scientific Research (A)
    • Review Section
      Medium-sized Section 60:Information science, computer engineering, and related fields
    • Research Institution
      Tohoku University
  •  脳型コンピューティング向けダーク・シリコンロジックLSIの基盤技術開発

    • Principal Investigator
      羽生 貴弘
    • Project Period (FY)
      2016
    • Research Category
      Grant-in-Aid for Scientific Research (A)
    • Research Field
      Computer system
    • Research Institution
      Tohoku University
  •  Fundamental Technology Development of Dark-Silicon Logic LSI for Brain-Inspired Computing

    • Principal Investigator
      Hanyu Takahiro
    • Project Period (FY)
      2016 – 2020
    • Research Category
      Grant-in-Aid for Scientific Research (S)
    • Research Field
      Computer system
    • Research Institution
      Tohoku University
  •  New Approach to Design of Transition Signaling Asynchronous CircuitsPrincipal Investigator

    • Principal Investigator
      Yoneda Tomohiro
    • Project Period (FY)
      2015 – 2017
    • Research Category
      Grant-in-Aid for Challenging Exploratory Research
    • Research Field
      Computer system
    • Research Institution
      National Institute of Informatics
  •  Study on Implementation for Greatly Reducing Power Dissipation of Serial Communication MechanismsPrincipal Investigator

    • Principal Investigator
      YONEDA Tomohiro
    • Project Period (FY)
      2015 – 2017
    • Research Category
      Grant-in-Aid for Scientific Research (A)
    • Research Field
      Communication/Network engineering
    • Research Institution
      National Institute of Informatics
  •  Optimization techniques for asynchronous circuit designPrincipal Investigator

    • Principal Investigator
      YONEDA Tomohiro
    • Project Period (FY)
      2011 – 2014
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      Computer system/Network
    • Research Institution
      National Institute of Informatics
  •  A Fundamental Study on Hardware Accelerator for SVGPrincipal Investigator

    • Principal Investigator
      YONEDA Tomohiro
    • Project Period (FY)
      2008 – 2010
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      Computer system/Network
    • Research Institution
      National Institute of Informatics
  •  Research on an efficient analysis method of real-time software based on a level oriented net modelPrincipal Investigator

    • Principal Investigator
      YONEDA Tomohiro
    • Project Period (FY)
      2003 – 2004
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      Software
    • Research Institution
      National Institute of Informatics
  •  多値技術に基づく高速データ転送とそのマルチメディアVLSIプロセッサへの応用

    • Principal Investigator
      Hanyu Takahiro
    • Project Period (FY)
      2002
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      計算機科学
    • Research Institution
      Tohoku University
  •  Verification methods of secure systems based on logical specifications

    • Principal Investigator
      YONEZAKI Naoki
    • Project Period (FY)
      2000 – 2003
    • Research Category
      Grant-in-Aid for Scientific Research on Priority Areas
    • Review Section
      Science and Engineering
    • Research Institution
      Tokyo Institute of Technology
  •  Research on a synthesis and verification tool for high performance asynchronous circuitsPrincipal Investigator

    • Principal Investigator
      YONEDA Tomohiro
    • Project Period (FY)
      2000 – 2002
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      計算機科学
    • Research Institution
      National Institute of Informatics
      Tokyo Institute of Technology
  •  Research on formal verification of asynchronous logic circuits with bounded delaysPrincipal Investigator

    • Principal Investigator
      YONEDA Tomohiro
    • Project Period (FY)
      1997 – 1998
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      計算機科学
    • Research Institution
      TOKYO INSTITUTE OF TECHNOLOGY
  •  定理証明方式に基づく非同期式回路の検証に関する研究Principal Investigator

    • Principal Investigator
      米田 友洋
    • Project Period (FY)
      1996
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      計算機科学
    • Research Institution
      Tokyo Institute of Technology
  •  Study on Implementation and Evaluation of High-performance Asynchronous Microprocessor

    • Principal Investigator
      NANYA Takashi
    • Project Period (FY)
      1995 – 1996
    • Research Category
      Grant-in-Aid for Scientific Research (A)
    • Research Field
      計算機科学
    • Research Institution
      The University of Tokyo
      Tokyo Institute of Technology
  •  非同期式プロセッサの設計検証システムに関する研究Principal Investigator

    • Principal Investigator
      米田 友洋
    • Project Period (FY)
      1994
    • Research Category
      Grant-in-Aid for General Scientific Research (C)
    • Research Field
      計算機科学
    • Research Institution
      Tokyo Institute of Technology
  •  Investigation of the Actual Conditions of the Academic Research in Japan

    • Principal Investigator
      NOYORI Ryoji
    • Project Period (FY)
      1994 – 1995
    • Research Category
      Grant-in-Aid for Co-operative Research (A)
    • Research Institution
      Nagoua University
  •  リアルタイムシステムのための階層的時間検証方式に関する研究Principal Investigator

    • Principal Investigator
      米田 友洋
    • Project Period (FY)
      1993
    • Research Category
      Grant-in-Aid for Encouragement of Young Scientists (A)
    • Research Field
      計算機科学
    • Research Institution
      Tokyo Institute of Technology
  •  Study on Architecture and Design Methdology of Asynchronous Processors

    • Principal Investigator
      NANYA Takashi
    • Project Period (FY)
      1992 – 1993
    • Research Category
      Grant-in-Aid for General Scientific Research (B)
    • Research Field
      情報工学
    • Research Institution
      Tokyo Institute of Technology
  •  Research on Automatic Synthesis of Self-Checking Processors.

    • Principal Investigator
      NANYA Takashi
    • Project Period (FY)
      1990 – 1991
    • Research Category
      Grant-in-Aid for General Scientific Research (B)
    • Research Field
      情報工学
    • Research Institution
      Tokyo Institute of Technology
  •  セルフチェッキング機能に基づくVLSIテスト方式に関する研究

    • Principal Investigator
      南谷 崇
    • Project Period (FY)
      1988 – 1989
    • Research Category
      Grant-in-Aid for General Scientific Research (C)
    • Research Field
      計算機工学
    • Research Institution
      Tokyo Institute of Technology
  •  Research on Self-Checking VLSI ProcessorsPrincipal Investigator

    • Principal Investigator
      YONEDA Tomohiro, 南谷 崇
    • Project Period (FY)
      1985 – 1986
    • Research Category
      Grant-in-Aid for General Scientific Research (B)
    • Research Field
      計算機工学
    • Research Institution
      Tokyo Institute of Technology

All 2018 2017 2016 2015 2011 2010 2003 Other

All Journal Article Presentation

  • [Journal Article] MTJ-Based Asynchronous Circuits for Re-Initialization Free Computing against Power Failures2018

    • Author(s)
      N. Onizawa, M. Imai, T. Yoneda, and T. Hanyu
    • Journal Title

      Microelectronics Journal

      Volume: 82 Pages: 46-61

    • DOI

      10.1016/j.mejo.2018.10.012

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Journal Article] Asynchronous Pipeline Controller Based on Early Acknowledgement Protocol2010

    • Author(s)
      C.Mannakkara, T.Yoneda
    • Journal Title

      電子情報通信学会英文論文誌

      Volume: E93-D,No.8 Pages: 2145-2161

    • NAID

      10027364654

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-20500059
  • [Journal Article] Partial Order Reduction for Timed Circuit Verification Based on a Level Oriented Model2003

    • Author(s)
      Tomoya Kitai, Yusuke Oguro, Tomohiro Yoneda, Eric Mercer, Chris Myers
    • Journal Title

      Proc. of IEICE Vol.E86-D No.12

      Pages: 2601-2611

    • NAID

      10012560062

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-15300009
  • [Journal Article] Failure Trace analysis of Timed Circuits for Automatic Timing Constraints Derivation

    • Author(s)
      Tomoya Kitai, Tomohiro Yoneda, Chris Myers
    • Journal Title

      Proc. of IEICE (to appear)

    • NAID

      110003502000

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-15300009
  • [Journal Article] Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits

    • Author(s)
      Denduang Pradubsuwun, Tomohiro Yoneda, Chris Myers
    • Journal Title

      電子情報通信学会英文論文誌 (採録決定済み)

    • NAID

      110003173584

    • Data Source
      KAKENHI-PROJECT-15300009
  • [Journal Article] Asynchronous Pipeline Controller Based on Early Acknowledgement Protocol

    • Author(s)
      C.Mannakkara, T.Yoneda
    • Journal Title

      電子情報通信学会英文論文誌 E93-D, No.8

      Pages: 2145-2161

    • NAID

      10027364654

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-20500059
  • [Journal Article] Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits

    • Author(s)
      Denduang Pradubsuwun, Tomohiro Yoneda, Chris Myers
    • Journal Title

      Proc. of IEICE (to appear)

    • NAID

      110003173584

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-15300009
  • [Presentation] Minimum Power Supply Asynchronous Circuits for Re-initialization Free Computing2018

    • Author(s)
      M. Imai, N. Onizawa, T. Hanyu, and T. Yoneda
    • Organizer
      21st Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Presentation] Novel Delay Elements for Bundled-Data Transfer Circuits Based on Two-Phase Handshaking Protocols2018

    • Author(s)
      Masashi Imai, Shinichiro Akasaka, Tomohiro Yoneda
    • Organizer
      24th IEEE International Symposium on Asynchronous Circuits and Systems
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15H02254
  • [Presentation] MTJ-Based Asynchronous Circuits for Re-initialization Free Computing against Power Failures2017

    • Author(s)
      N. Onizawa, M. Imai, T. Hanyu, and T. Yoneda
    • Organizer
      23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Presentation] The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs2016

    • Author(s)
      Masashi Imai; Thiem Van Chu; Kenji Kise; Tomohiro Yoneda
    • Organizer
      10t ACM/IEEE International Symposium on Networks-on-Chip
    • Place of Presentation
      奈良県奈良市,奈良春日野国際フォーラム
    • Year and Date
      2016-08-31
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15K12005
  • [Presentation] The Synchronous vs. Asynchronous NoC Routers: An Apple-to-Apple Comparison between Synchronous and Transition Signaling Asynchronous Designs2016

    • Author(s)
      Masashi Imai, Thiem Van Chu, Kenji Kise and Tomohiro Yoneda
    • Organizer
      10th ACM/IEEE International Symposium on Networks-on-Chip
    • Place of Presentation
      奈良県奈良市,奈良春日野国際フォーラム
    • Year and Date
      2016-08-31
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15K12005
  • [Presentation] Power-Gated Single-Track Asynchronous Circuits Using Three-Terminal MTJ-Based Nonvolatile Devices for Energy Harvesting Systems2016

    • Author(s)
      Tomohiro Yoneda, Naoya Onizawa, Masashi Imai, Takahiro Hanyu,
    • Organizer
      Async2016 Fresh ideas track
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Presentation] Improvement of Line Coding Overhead Targeting Both Run-Length and DC-Balance2016

    • Author(s)
      Sarat Yoowattana, Tomohiro Yoneda
    • Organizer
      IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip
    • Place of Presentation
      Lyon Congress Center, Lyon, France
    • Year and Date
      2016-09-21
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15H02254
  • [Presentation] A New Encoding Mechanism for Low Power Inter-Chip Serial Communication in Asynchronous Circuits2015

    • Author(s)
      Tomohiro Yoneda, Masashi Imai
    • Organizer
      The 33rd IEEE International Conference on Computer Design
    • Place of Presentation
      New York University, New York City, USA
    • Year and Date
      2015-10-18
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15H02254
  • [Presentation] Dependability Techniques for Networks on Chips2011

    • Author(s)
      T.Yoneda
    • Organizer
      IFIP WG 10.4 60^<th> meeting
    • Place of Presentation
      Taoyuan, Taiwan(招待講演)
    • Year and Date
      2011-07-02
    • Data Source
      KAKENHI-PROJECT-23300020
  • [Presentation] Asynchronous Network-on-Chip and its potential2011

    • Author(s)
      T.Yoneda
    • Organizer
      The 11th International Conference on Application of Concurrency to System Design
    • Place of Presentation
      Newcastle upon Tyne, UK(招待講演)
    • Year and Date
      2011-06-22
    • Data Source
      KAKENHI-PROJECT-23300020
  • [Presentation] An NoC-based Evaluation Platform for Safety-Critical Automotive Applications

    • Author(s)
      Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Takahiro Hanyu, Kenji Kise, Yuichi Nakamura
    • Organizer
      APCCAS2014
    • Place of Presentation
      ANAインターコンチネンタル石垣リゾート( 沖縄県石垣市)
    • Year and Date
      2014-11-17 – 2014-11-20
    • Data Source
      KAKENHI-PROJECT-23300020
  • [Presentation] Multiple-Clock Multiple-Edge-Triggered Multiple-Bit Flip-flops for Two-Phase Handshaking Asynchronous Circuits

    • Author(s)
      Masashi Imai, Tomohiro Yoneda
    • Organizer
      ISCAS2014
    • Place of Presentation
      オーストラリア,メルボルン
    • Year and Date
      2014-06-01 – 2014-06-04
    • Data Source
      KAKENHI-PROJECT-23300020
  • [Presentation] A Floorplan Method for SDI-model-based Asynchronous Circuits to Achieve High Robustness against Delay Variations

    • Author(s)
      Masashi Imai, Tomohiro Yoneda
    • Organizer
      IEEE/ACM Workshop on CAD for Multi-Synchronous and Asynchronous Circuits and Systems 2012
    • Place of Presentation
      San Jose, CA, USA
    • Data Source
      KAKENHI-PROJECT-23300020
  • 1.  NANYA Takashi (80143684)
    # of Collaborated Projects: 6 results
    # of Collaborated Products: 0 results
  • 2.  Hanyu Takahiro (40192702)
    # of Collaborated Projects: 5 results
    # of Collaborated Products: 4 results
  • 3.  TOHMA Yoshihiro (50016317)
    # of Collaborated Projects: 4 results
    # of Collaborated Products: 0 results
  • 4.  今井 雅 (70323665)
    # of Collaborated Projects: 4 results
    # of Collaborated Products: 6 results
  • 5.  FUJIWARA Eiji (20211526)
    # of Collaborated Projects: 3 results
    # of Collaborated Products: 0 results
  • 6.  鬼沢 直哉 (90551557)
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 4 results
  • 7.  夏井 雅典 (10402661)
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 0 results
  • 8.  TAKAHASHI Ryuichi (30236335)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 9.  NOYORI Ryoji (50022554)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 10.  TANAKA Akita (70171733)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 11.  WAKATUKI Yoshio (40220826)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 12.  OGAWA Haruko (90143700)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 13.  MIZUMOTO Tetsuya (00174045)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 14.  HAYANO Ryugo (30126148)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 15.  KAGOTANI Hiroto (50271060)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 16.  UENO Yoichiro (70262285)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 17.  YONEZAKI Naoki (00126286)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 18.  YOSHIURA Noriaki (00302969)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 19.  NISHIZAKI Shin-ya (90263615)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 20.  TOMOISHI Masahiko (60262284)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 21.  川人 祥二 (40204763)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 22.  亀山 充隆 (70124568)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 23.  難波 成任 (50189221)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 24.  野間 竜男 (20180771)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 25.  吉瀬 謙二 (50323887)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 26.  齋藤 寛 (50361671)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 27.  池田 正二 (90281865)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 28.  村口 正和 (90386623)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 29.  FUKUMA Masao
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 30.  山田 八郎
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results

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